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Interconnect Noise Optimization in Nanometer Technologies

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Interconnect Noise Optimization in Nanometer Technologies Cover

 

Synopses & Reviews

Publisher Comments:

Interconnect has become the dominating factor in determining system performance in nanometer technologies. This book is dedicated to this important subject. The primary purpose of this monograph is to provide insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits. In this monograph, the effects of wire size, spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), frequency, shields, direction of the signals, and wire width for both the aggressors and the victim wires on system performance and reliability is thoroughly investigated. Also, parameters like driver strength has been considered as several recent studies considered the simultaneous device and interconnect sizing. Crosstalk noise, as well as the impact of coupling on aggressor delay is analyzed. The pulse width of the crosstalk noise, which is of similar importance for circuit performance as the peak amplitude, is also analyzed. We have considered more parameters that can affect the signal integrity and presented practical intensive simulation results. This book brings together a wealth of information previously scattered throughout the literature, presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. The practical aspects of the algorithms and models are explained with sufficient detail. It deeply investigates the most two effective parameters in layout optimization, spacing and shield insertion, that can affect both capacitive and inductive noise. Noise models needed for layouts with multi-layer multi-crosscoupling segments are investigated. Different post-layout optimization techniques are explained with complexity analysis and benchmarks tests are provided.

Synopsis:

Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnect Provides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits

Synopsis:

Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits. The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.

Table of Contents

Introduction.- Noise Analysis and Design in Deep Submicron.- Interconnect Noise Analysis and Optimization Techniques.- Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies.- Minimum Area Shield Insertion for Inductive Noise Reduction.- Spacing Algorithms for Crosstalk Noise Reduction.- Post Layout Interconnect Optimization for Crosscoupling Noise Reduction.- 3D Integration. - EDA Industry Tools: State of the Art.

Product Details

ISBN:
9780387258706
Author:
Elgamel, Mohamed
Publisher:
Springer
Author:
Elgamel, Mohamed A.
Author:
Bayoumi, Magdy A.
Author:
Bayoumi, Magdy
Subject:
Engineering - Electrical & Electronic
Subject:
Electronics - Circuits - General
Subject:
CAD-CAM - General
Subject:
Algorithms
Subject:
Electronic noise
Subject:
Crosstalk.
Subject:
Interconnect
Subject:
Shield insertion
Subject:
Wire spacing
Subject:
Electricity
Subject:
Interconnects (Integrated circuit technology)
Subject:
Circuits and Systems
Subject:
Computer-Aided Engineering (CAD, CAE) and Design
Subject:
Computer: Hardware
Subject:
Electrical Engineering <P>This book provides insight into the use of CAD for layout analysis and optimization of interconnect in high speed, high complexity integrated circuits, which have become the dominating factor in determining system performance in
Subject:
Electrical engineering
Subject:
Electricity-General Electronics
Copyright:
Edition Number:
1
Edition Description:
Book
Publication Date:
November 2005
Binding:
HARDCOVER
Language:
English
Illustrations:
Y
Pages:
156
Dimensions:
235 x 155 mm

Related Subjects

Computers and Internet » Operating Systems » Microsoft Windows » Windows 95 » Applications
Engineering » Engineering » CAD
History and Social Science » Economics » General
Science and Mathematics » Biology » Cytology and Cell Biology
Science and Mathematics » Electricity » General Electricity
Science and Mathematics » Electricity » General Electronics
Science and Mathematics » Electricity » Solid State Electronics

Interconnect Noise Optimization in Nanometer Technologies Sale Hardcover
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Product details 156 pages Springer - English 9780387258706 Reviews:
"Synopsis" by , Presents a range of CAD algorithms and techniques for synthesizing and optimizing interconnect Provides insight & intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits
"Synopsis" by , Interconnect has become the dominating factor in determining system performance in nanometer technologies. Dedicated to this subject, Interconnect Noise Optimization in Nanometer Technologies provides insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits. The authors bring together a wealth of information presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. Practical aspects of the algorithms and the models are explained with sufficient details. The book investigates the most effective parameters in layout optimization. Different post-layout optimization techniques with complexity analysis and benchmarks tests are provided. The impact crosstalk noise and coupling on the wire delay is analyzed. Parameters that affect signal integrity are also considered.
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