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Gabrielle ZevinThe American Booksellers Association collects nominations from bookstores all over the country for favorite forthcoming titles. The Storied Life of... Continue »
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Formal Semantics and Proof Techniques for Optimizing VHDL Models

by

Formal Semantics and Proof Techniques for Optimizing VHDL Models Cover

 

Synopses & Reviews

Publisher Comments:

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

Book News Annotation:

Presents a formal model of the hardware description language, VHDL, to help specify and clarify aspects of it that have remained incomplete or variously interpreted because of the informal English semantics used with it. The model specifies both the static and dynamic semantics, provides a mathematical framework for representing constructs and shows how those constructs can be formally manipulated to reason about the language, presents the dynamic semantics as a description of what the simulation of VHDL means, and specifies what values the signals of a VHDL description would take if the description were to be executed.
Annotation c. Book News, Inc., Portland, OR (booknews.com)

Synopsis:

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Description:

Includes bibliographical references (p. [151]-155) and index.

Table of Contents

1. Introduction. 2. Related Work. 3. The Static Model. 4. A Well-Formed VHDL Model. 5. The Reduction Algebra. 6. Completeness of the Reduced Form. 7. Interval Temporal Logic. 8. The Dynamic Model. 9. Applications of the Dynamic Model. 10. A Framework for Proving Equivalences Using PVS. 11. Conclusions. Appendices. References. Index.

Product Details

ISBN:
9780792383758
Author:
Umamageswaran, Kothanda
Author:
Pandey, Sheetanshu L.
Author:
Umamageswaran, Kothanda
Author:
Umanageswaran, Kothanda
Author:
Wilsey, Philip A.
Publisher:
Springer
Location:
Boston
Subject:
General
Subject:
Engineering - Electrical & Electronic
Subject:
Programming Languages - General
Subject:
Electronics - Circuits - General
Subject:
VHDL (Computer hardware description language)
Subject:
VHDL
Subject:
Electricity
Subject:
Circuits and Systems
Subject:
Computer: Hardware
Subject:
Computer-Aided Engineering (CAD, CAE) and Design
Subject:
Electrical engineering
Subject:
Software Engineering - Programming and Languages
Copyright:
Edition Number:
1
Edition Description:
Book
Publication Date:
November 1998
Binding:
HARDCOVER
Language:
English
Illustrations:
Yes
Pages:
179
Dimensions:
235 x 155 mm 970 gr

Related Subjects

Computers and Internet » Software Engineering » Programming and Languages
Engineering » Communications » Telephony
Health and Self-Help » Health and Medicine » Medical Specialties
Science and Mathematics » Electricity » General Electricity
Science and Mathematics » Electricity » VHDL
Science and Mathematics » Mathematics » General

Formal Semantics and Proof Techniques for Optimizing VHDL Models Used Hardcover
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Product details 179 pages Kluwer Academic Publishers - English 9780792383758 Reviews:
"Synopsis" by , Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.
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