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PCI System Architecture (Mindshare PC System Architecture)

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Synopses & Reviews

Publisher Comments:

PCI System Architecture is a detailed and comprehensive guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for fast communication between peripheral devices and the computer processor.

This new edition has been thoroughly updated, reorganized, and expanded to cover the PCI Local Bus Specification version 2.2 and other recent developments, including the new PCI Hot-Plug Specification, changes to the PCI-to-PCI Bridge Architecture Specification, revisions to the PCI Bus Power Management Interface Specification, and the new features of the PCI BIOS Specification.

This book provides clear and concise explanations of the relationship of PCI to the rest of the system and PCI fundamentals, including commands, read and write transfers, memory and I/O addressing, error handling, interrupts, and configuration transactions and registers. In addition, you will find specific information on such key topics as:

  • Hot-Plug Specification
  • Power management
  • CompactPCI
  • The 64-bit PCI Extension
  • 66 MHz PCI Implementation
  • Expansion ROMs
  • PCI-to-PCI Bridge and the PCI BIOS
  • Add-in cards and connectors
  • Bus arbitration
  • Reflected-wave switching
  • Early transaction end
  • Fast back-to-back and stepping
Changes from PCI 2.1 to PCI 2.2 and changes from PCI-to-PCI Bridge Specification 1.0 to 1.1 are visibly highlighted throughout the book so that those familiar with the previous versions can quickly get a handle on new features and functions.

Anyone who designs or tests hardware or software involving the PCI bus will find PCI System Architecture, Fourth Edition a valuable resource for understanding and working with this important technology.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer1s perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

Book News Annotation:

A detailed guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for communication between peripheral devices and the computer processor. Explains the relationship of PCI to the rest of the system, and covers PCI fundamentals and changes between versions. This fourth edition has been expanded to cover the PCI Local Bus Specification version 2.2. For hardware and software design and support personnel familiar with PC and processor bus architecture. Shanley is an authority on PC system architecture. Anderson trains engineers, programmers, and technicians.
Annotation c. Book News, Inc., Portland, OR (booknews.com)

Synopsis:

PCI System Architecture is a detailed and comprehensive guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for fast communication between peripheral devices and the computer processor.

This new edition has been thoroughly updated, reorganized, and expanded to cover the PCI Local Bus Specification version 2.2 and other recent developments, including the new PCI Hot-Plug Specification, changes to the PCI-to-PCI Bridge Architecture Specification, revisions to the PCI Bus Power Management Interface Specification, and the new features of the PCI BIOS Specification.

This book provides clear and concise explanations of the relationship of PCI to the rest of the system and PCI fundamentals, including commands, read and write transfers, memory and I/O addressing, error handling, interrupts, and configuration transactions and registers. In addition, you will find specific information on such key topics as:

  • Hot-Plug Specification
  • Power management
  • CompactPCI
  • The 64-bit PCI Extension
  • 66 MHz PCI Implementation
  • Expansion ROMs
  • PCI-to-PCI Bridge and the PCI BIOS
  • Add-in cards and connectors
  • Bus arbitration
  • Reflected-wave switching
  • Early transaction end
  • Fast back-to-back and stepping

Changes from PCI 2.1 to PCI 2.2 and changes from PCI-to-PCI Bridge Specification 1.0 to 1.1 are visibly highlighted throughout the book so that those familiar with the previous versions can quickly get a handle on new features and functions.

Anyone who designs or tests hardware or software involving the PCI bus will find PCI System Architecture, Fourth Edition a valuable resource for understanding and working with this important technology.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer's perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

Synopsis:

PCI is Intel's local bus standard and the bus continues to be utilized throughout the computer industry. The fourth edition reflects revision 2.2 of the PCI specification, and is very timely. Two of the expected changes are the inclusion of power management and the expansion of the Vital Product Data area. As one of the authors described, "Very important that the engineer work with the latest info".

About the Author

MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.

Tom Shanley, president of MindShare, Inc., is one of the world's foremost authorities on computer system architecture. In the course of his career, he has trained thousands of engineers in hardware and software design.

Don Anderson is the author of many MindShare books. He passes on his wealth of experience in digital electronics and computer design by training engineers, programmers, and technicians for MindShare.

Table of Contents


About This Book
The MindShare Architecture Series
Organization of This Book
Designation of Specification Changes
Cautionary Note
Who this Book is For
Prerequisite Knowledge
Object Size Designations
Documentation Conventions
Hex Notation
Binary Notation
Decimal Notation
Signal Name Representation
Identification of Bit Fields (logical groups of bits or signals)
We Want Your Feedback

Chapter 1: Intro To PCI

PCI Bus History
PCI Bus Features
PCI Device vs.... Function
Specifications Book is Based On
Obtaining PCI Bus Specification(s)

Chapter 2: Intro to PCI Bus Operation

Burst Transfer
Initiator, Target and Agents
Single- Vs. Multi-Function PCI Devices
PCI Bus Clock
Address Phase
Claiming the Transaction
Data Phase(s)
Transaction Duration
Transaction Completion and Return of Bus to Idle State
Response to Illegal Behavior
"Green" Machine

Chapter 3: Intro to Reflected-Wave Switching

Each Trace Is a Transmission Line
Old Method: Incident-Wave Switching
PCI Method: Reflected-Wave Switching
CLK Signal
RST#/REQ64# Timing
Slower Clock Permits Longer Bus

Chapter 4: The Signal Groups

Introduction
System Signals
PCI Clock Signal (CLK)
CLKRUN# Signal
Description
Achieving CLKRUN# Benefit On Add-In Cards
Reset Signal (RST#)
Address/Data Bus, Command Bus, and Byte Enables
Preventing Excessive Current Drain
Transaction Control Signals
Arbitration Signals
Interrupt Request Signals
Error Reporting Signals
Data Parity Error
System Error
Cache Support (Snoop Result) Signals
64-bit Extension Signals
Resource Locking
JTAG/Boundary Scan Signals
Interrupt Request Pins
PME# and 3.3 Vaux
Sideband Signals
Signal Types
Device Cannot Simultaneously Drive and Receive a Signal
Central Resource Functions
Subtractive Decode (by ISA Bridge)
Background
Tuning Subtractive Decoder
Reading Timing Diagrams

Chapter 5: PCI Bus Arbitration

Arbiter
Arbitration Algorithm
Example Arbiter with Fairness
Master Wishes To Perform More Than One Transaction
Hidden Bus Arbitration
Bus Parking
Request/Grant Timing
Example of Arbitration Between Two Masters
State of REQ# and GNT# During RST#
Pullups On REQ# From Add-In Connectors
Broken Master

Chapter 6: Master and Target Latency

Mandatory Delay Before First Transaction Initiated
Bus Access Latency
Pre-2.1 Devices Can Be Bad Boys
Preventing Master from Monopolizing the Bus
Master Must Transfer Data Within 8 CLKs
IRDY# Deasserted In Clock After Last Data Transfer
Latency Timer Keeps Master From Monopolizing Bus
Location and Purpose of Master Latency Timer
How LT Works
Is Implementation of LT Register Mandatory?
Can LT Value Be Hardwired?
How Does Software Determine Timeslice To Be Allocated To Master?
Treatment of Memory Write and Invalidate Command
Preventing Target From Monopolizing Bus
General
Target Must Transfer Data Expeditiously
General
The First Data Phase Rule
General
Master's Response To Retry
Sometimes Target Can't Transfer First Data Within 16 CLKs
Target Frequently Can't Transfer First Data Within 16 CLKs
Two Exceptions To First Data Phase Rule
Subsequent Data Phase Rule
General
In Data Phase and Cannot Transfer Data Within 8 Clocks
OK In This Data Phase, But Can't Meet Rule In Next One
Master's Response To a Disconnect
Target's Subsequent Latency and Master's Latency Timer
Target Latency During Initialization Time
Initialization Time vs....Run Time
Definition of Initialization Time and Behavior (Before 2.2)
Definition of Initialization Time and Behavior (2.2)
Delayed Transactions
The Problem
The Solution
Information Memorized
Master and Target Actions During Delayed Transaction
Commands That Can Use Delayed Transactions
Request Not Completed and Targeted Again
Special Cycle Monitoring While Processing Request
Discard of Delayed Requests
Multiple Delayed Requests from Same Master
Request Queuing In Target
Discard of Delayed Completions
Read From Prefetchable Memory
Master Tardy In Repeating Transaction
Reporting Discard of Data On a Read
Handling Multiple Data Phases
Master or Target Abort Handling
What Is Prefetchable Memory?
Delayed Read Prefetch

Posting Improves Memory Write Performance
General
Combining
Byte Merging
Collapsing Is Forbidden
Memory Write Maximum Completion Limit
Transaction Ordering and Deadlocks

Chapter 7: The Commands

Introduction
Interrupt Acknowledge Command
Introduction
Background
Host/PCI Bridge Handling of Interrupt Acknowledge
PCI Interrupt Acknowledge Transaction
PowerPC PReP Handling of INTR
Special Cycle Command
General
Special Cycle Generation Under Software Control
Special Cycle Transaction

Single-Data Phase Special Cycle Transaction
Multiple Data Phase Special Cycle Transaction

IO Read and Write Commands
Accessing Memory
Target Support For Bulk Commands Is Optional
Cache Line Size Register And the Bulk Commands
Bulk Commands Are Optional Performance Enhancement Tools
Bridges Must Discard Prefetched Data Not Consumed By Master
Writing Memory

Memory Write Command
Memory Write-and-Invalidate Command
Problem
Description of Memory Write-and-Invalidate Command

More Information On Memory Transfers
Configuration Read and Write Commands
Dual-Address Cycle
Reserved Bus Commands

Chapter 8: Read Transfers

Some Basic Rules For Both Reads and Writes
Parity
Example Single Data Phase Read
Example Burst Read
Treatment of Byte Enables During Read or Write
Byte Enables Presented on Entry To Data Phase
Byte Enables May Change In Each Data Phase
Data Phase with No Byte Enables Asserted
Target with Limited Byte Enable Support
Rule for Sampling of Byte Enables
Cases Where Byte Enables Can Be Ignored
Performance During Read Transactions

Chapter 9: Write Transfers

Example Single Data Phase Write Transaction
Example Burst Write Transaction
Performance During Write Transactions

Chapter 10: Memory and IO Addressing

Memory Addressing
The Start Address
Addressing Sequence During Memory Burst

Linear (Sequential) Mode
Cache Line Wrap Mode
When Target Doesn't Support Setting on AD[1:0]

PCI IO Addressing
Do Not Merge Processor IO Writes
General
Decode By Device That Owns Entire IO Dword
Decode by Device With 8-Bit or 16-Bit Ports
Unsupported Byte Enable Combination Results in Target Abort
Null First Data Phase Is Legal
IO Address Management

X86 Processor Cannot Perform IO Burst
Burst IO Address Counter Management

When IO Target Doesn't Support Multi-Data Phase Transactions
Legacy IO Decode

When Legacy IO Device Owns Entire Dword
When Legacy IO Device Doesn't Own Entire Dword

Chapter 11: Fast Back-to-Back & Stepping
Fast Back-to-Back Transactions
Decision to Implement Fast Back-to-Back Capability
Scenario 1: Master Guarantees Lack of Contention

1st Must Be Write, 2nd Is Read or Write, But Same Target
How Collision Avoided On Signals Driven By Target
How Targets Recognize New Transaction Has Begun
Fast Back-to-Back and Master Abort

Scenario Two: Targets Guarantee Lack of Contention
Address/Data Stepping
Advantages: Diminished Current Drain and Crosstalk
Why Targets Don't Latch Address During Stepping Process
Data Stepping
How Device Indicates Ability to Use Stepping
Designer May Step Address, Data, PAR (and PAR64) and IDSEL
Continuous and Discrete Stepping
Disadvantages of Stepping
Preemption While Stepping in Progress
Broken Master.
Stepping Example
When Not to Use Stepping
Who Must Support Stepping?

Chapter 12: Early Transaction End

Introduction
Master-Initiated Termination
Master Preempted

Introduction
Preemption During Timeslice
Timeslice Expiration Followed by Preemption

Master Abort: Target Doesn't Claim Transaction

Introduction
Addressing Non-Existent Device
Normal Response To Special Cycle Transaction
Configuration Transaction Unclaimed
No Target Will Claim Transaction Using Reserved Command
Master Abort On Single vs....Multiple-Data Phase Transaction
Master Abort on Single Data Phase Transaction
Master Abort on Multi-Data Phase Transaction
Action Taken by Master in Response to Master Abort
General
Master Abort On Special Cycle Transaction
Master Abort On Configuration Access

Target-Initiated Termination
STOP# Signal Puts Target In the Driver's Seat
STOP# Not Permitted During Turn-Around Cycle
Disconnect

Resumption of Disconnected Transaction Is Optional
Reasons Target Issues Disconnect
Target Slow to Complete Subsequent Data Phase
Target Doesn't Support Burst Mode
Memory Target Doesn't Understand Addressing Sequence
Transfer Crosses Over Target's Address Boundary
Burst Memory Transfer Crosses Cache Line Boundary
Disconnect With Data Transfer (A and B)
Disconnect A
Disconnect B
Disconnect Without Data Transfer
Disconnect Without Data Transfer-Type 1
Disconnect Without Data Transfer-Type 2

Retry

Reasons Target Issues Retry
Target Very Slow to Complete First Data Phase
Snoop Hit on Modified Cache Line
Resource Busy
Bridge Locked
Description of Retry
Retry Issued and IRDY# Already Asserted
Retry Issued and IRDY# Not Yet Asserted

Target Abort

Description
Some Reasons Target Issues Target Abort
Broken Target
I/O Addressing Error
Address Phase Parity Error
Master Abort on Other Side of PCI-to-PCI Bridge
Master's Response to Target Abort
Target Abort Example

After Retry/Disconnect, Repeat Request ASAP

General
Behavior of Device Containing Multiple Masters

Target-Initiated Termination Summary

Chapter 13: Error Detection and Handling

Status Bit Name Change
Introduction to PCI Parity
PERR# Signal
Data Parity
Data Parity Generation and Checking on Read

Introduction
Example Burst Read
Data Parity Generation and Checking on Write
Introduction
Example Burst Write
Data Parity Reporting
General
Master Can Choose Not To Assert PERR#
Parity Error During Read
Important Note Regarding Chipsets That Monitor PERR#
Parity Error During Write
Data Parity Error Recovery
Special Case: Data Parity Error During Special Cycle
Devices Excluded from PERR# Requirement
Chipsets
Devices That Don't Deal with OS/Application Program or Data

SERR# Signal

Address Phase Parity
Address Phase Parity Generation and Checking
Address Phase Parity Error Reporting
System Errors
General
Address Phase Parity Error
Data Parity Error During Special Cycle
Master of MSI Receives an Error
Target Abort Detection
Other Possible Causes of System Error
Devices Excluded from SERR# Requirement

Chapter 14: Interrupts

Three Ways To Deliver Interrupts To Processor
Using Pins vs....Using MSI Capability
Single-Function PCI Device
Multi-Function PCI Device
Connection of INTx# Pins To System Board Traces
Interrupt Routing
General
Routing Recommendation In PCI Specification
BIOS "Knows" Interrupt Trace Layout
Well-Designed Chipset Has Programmable Interrupt Router
Interrupt Routing Information
Interrupt Routing Table
General
Finding the Table
PCI Interrupts Are Shareable
Hooking the Interrupt
Interrupt Chaining
General
Step 1: Initialize All Entries To Point To Dummy Handler
Step 2: Initialize All Entries For Embedded Devices
Step 3: Hook Entries For Embedded Device BIOS Routines
Step 4: Perform Expansion Bus ROM Scan
Step 5: Perform PCI Device Scan
Step 6: Load OS
Step 7: OS Loads and Call Drivers' Initialization Code
Linked-List Has Been Built for Each Interrupt Level
Servicing Shared Interrupts
Example Scenario
Both Devices Simultaneously Generate Requests
Processor Interrupted and Requests Vector
First Handler Executed
Jump to Next Driver in Linked List
Jump to Dummy Handler: Control Passed Back to Interrupted Program
Implied Priority Scheme
Interrupts and PCI-to-PCI Bridges
Message Signaled Interrupts (MSI)

Introduction
Advantages of MSI Interrupts
Basics of MSI Configuration
Basics of Generating an MSI Interrupt Request
How Is the Memory Write Treated by Bridges?
Memory Already Sync'd When Interrupt Handler Entered
The Problem
The Old Way of Solving the Problem
How MSI Solves the Problem
Interrupt Latency
MSI Are Non-Shared
MSI Is a New Capability Type
Description of the MSI Capability Register Set
Capability ID
Pointer To Next New Capability
Message Control Register
Message Address Register
Message Data Register
Message Write Can Have Bad Ending
Retry or Disconnect
Master or Target Abort Received
Write Results In Data Parity Error
Some Rules, Recommendations, etc

Chapter 15: The 64-bit PCI Extension

64-bit Data Transfers and 64-bit Addressing: Separate Capabilities
64-Bit Extension Signals
64-bit Cards in 32-bit Add-in Connectors
Pullups Prevent 64-bit Extension from Floating When Not in Use
Problem: a 64-bit Card in a 32-bit PCI Connector
How 64-bit Card Determines Type of Slot Installed In
64-bit Data Transfer Capability

Only Memory Commands May Use 64-bit Transfers
Start Address Quadword-Aligned
64-bit Target's Interpretation of Address
32-bit Target's Interpretation of Address
64-bit Initiator and 64-bit Target
64-bit Initiator and 32-bit Target
Null Data Phase Example
32-bit Initiator and 64-bit Target
Performing One 64-bit Transfer
With 64-bit Target
With 32-bit Target
Simpler and Just as Fast: Use 32-bit Transfers
With Known 64-bit Target
Disconnect on Initial Data Phase

64-bit Addressing

Used to Address Memory Above 4GB
Introduction
64-bit Addressing Protocol
64-bit Addressing by 32-bit Initiator
64-bit Addressing by 64-bit Initiator
32-bit Initiator Addressing Above 4GB
Subtractive Decode Timing Affected
Master Abort Timing Affected
Address Stepping
FRAME# Timing in Single Data Phase Transaction

64-bit Parity

Address Phase Parity
PAR64 Not Used for Single Address Phase
PAR64 Not Used for Dual-Address Phases by 32-bit Master
PAR64 Used for DAC by 64-bit Master When Requesting 64-bit Transfers
Data Phase Parity

Chapter 16: 66MHz PCI Implementation

Introduction
66MHz Uses 3.3V Signaling Environment
How Components Indicate 66MHz Support
66MHz-Capable Status Bit
M66EN Signal
How Clock Generator Sets Its Frequency
Does Clock Have to be 66MHz?
Clock Signal Source and Routing
Stopping Clock and Changing Clock Frequency
How 66MHz Components Determine Bus Speed
System Board with Separate Buses
Maximum Achievable Throughput
Electrical Characteristics
Latency Rule
66MHz Component Recommended Pinout
Adding More Loads and/or Lengthening Bus
Number of Add-In Connectors

Chapter 17: Intro to Configuration Address Space

Introduction
PCI Device vs....PCI Function
Three Address Spaces: I/O, Memory and Configuration
Host Bridge Needn't Implement Configuration Space
System with Single PCI Bus

Chapter 18: Configuration Transactions

Who Performs Configuration?
Bus Hierarchy
Introduction
Case 1: Target Bus Is PCI Bus 0
Case 2: Target Bus Is Subordinate To Bus 0
Must Respond To Config Accesses Within 2 25 Clocks After RST#
Intro to Configuration Mechanisms
Configuration Mechanism #1 (The Only Mechanism!)

Background
Configuration Mechanism #1 Description
General
Configuration Address Port
Bus Compare and Data Port Usage
Single Host/PCI Bridge
Multiple Host/PCI Bridges
Software Generation of Special Cycles

Configuration Mechanism #2 (is obsolete)
Basic Configuration #2 Mechanism
Configuration Space Enable, or CSE, Register
Forward Register
Support for Peer Bridges on Host Bus
Generation of Special Cycles
PowerPC PReP Configuration Mechanism
Type 0 Configuration Transaction

Address Phase
Implementation of IDSEL
Method One-IDSELs Routed Over Unused AD Lines
Method Two-IDSEL Output Pins/Traces
Resistive-Coupling Means Stepping In Type 0 Transactions

Data Phase Entered, Decode Begins
Type 0 Configuration Transaction Examples
Type 1 Configuration Transactions
Description
Special Cycle Request
Target Device Doesn't Exist
Configuration Burst Transactions Permitted
64-Bit Configuration Transactions Not Permitted

Chapter 19: Configuration Registers

Intro to Configuration Header Region
Mandatory Header Registers

Introduction
Registers Used to Identify Device's Driver
Vendor ID Register
Device ID Register
Subsystem Vendor ID and Subsystem ID Registers
Purpose of This Register Pair
Must Contain Valid Data When First Accessed
Revision ID Register
Class Code Register
General
Purpose of Class Code Register
Programming Interface Byte
Command Register
Status Register
Header Type Register

Other Header Registers

Introduction
Cache Line Size Register
Latency Timer: "Timeslice" Register
BIST Register
Base Address Registers (BARs)
Memory-Mapping Recommended
Memory Base Address Register
Decoder Width Field
Prefetchable Attribute Bit
Base Address Field
IO Base Address Register
Introduction
Description
PC-Compatible IO Decoder
Legacy IO Decoders
Determining Block Size and Assigning Address Range
How It Works
A Memory Example
An IO Example
Smallest/Largest Decoder Sizes
Smallest/Largest Memory Decoders
Smallest/Largest IO Decoders
Expansion ROM Base Address Register
CardBus CIS Pointer
Interrupt Pin Register
Interrupt Line Register
Min_Gnt Register: Timeslice Request
Max_Lat Register: Priority-Level Request

New Capabilities

Configuration Header Space Not Large Enough
Discovering That New Capabilities Exist
What the New Capabilities List Looks Like
AGP Capability
AGP Status Register
AGP Command Register
Vital Product Data (VPD) Capability
Introduction
It's Not Really Vital
What Is VPD?
Where Is the VPD Really Stored?
VPD On Cards vs....Embedded PCI Devices
How Is VPD Accessed?
Reading VPD Data
Writing VPD Data
Rules That Apply To Both Read and Writes
VPD Data Structure Made Up of Descriptors and Keywords
VPD Read-Only Descriptor (VPD-R) and Keywords
Is Read-Only Checksum Keyword Mandatory?
VPD Read/Write Descriptor (VPD-W) and Keywords
Example VPD List

User-Definable Features (UDF)

Chapter 20: Expansion ROMs

ROM Purpose-Device Can Be Used In Boot Process
ROM Detection
ROM Shadowing Required
ROM Content

Multiple Code Images
Format of a Code Image
General
ROM Header Format
ROM Signature
Processor/Architecture Unique Data
Pointer to ROM Data Structure
ROM Data Structure Format
ROM Signature
Vendor ID field in ROM data structure
Device ID in ROM data structure
Pointer to Vital Product Data (VPD)
PCI Data Structure Length
PCI Data Structure Revision
Class Code
Image Length
Revision Level of Code/Data
Code Type
Indicator Byte

Execution of Initialization Code

Introduction to Open Firmware
Introduction
Universal Device Driver Format
Passing Resource List To Plug-and-Play OS
BIOS Calls Bus Enumerators For Different Bus Environments
BIOS Selects Boot Devices and Finds Drivers For Them
BIOS Boots Plug-and-Play OS and Passes Pointer To It
OS Locates and Loads Drivers and Calls Init Code In each

Vital Product Data (VPD)
Moved From ROM to Configuration Space in 2.2
VPD Implementation in 2.1 Spec
Data Structure

Chapter 21: Add-in Cards and Connectors

Add-In Connectors

32- and 64-bit Connectors
32-bit Connector
Card Present Signals
REQ64# and ACK64#
64-bit Connector
3.3V and 5V Connectors
Universal Card
Shared Slot
Riser Card
Snoop Result Signals on Add-in Connector

PME# and 3.3Vaux
Add-In Cards
3.3V, 5V and Universal Cards
Long and Short Form Cards
Small PCI (SPCI)
Component Layout
Maintain Integrity of Boundary Scan Chain
Card Power Requirement
Maximum Card Trace Lengths
One Load per Shared Signal

Chapter 22: Hot-Plug PCI

The Problem
The Solution
No Changes To Adapter Cards
Software Elements
General
System Start Up
Hardware Elements
General
Attention Indicator and Optional Slot State Indicator
Option-Power Fault Detector
Option-Tracking System Power Usage
Card Removal and Insertion Procedures

On and Off States
Definition of On and Off
Turning Slot On
Turning Slot Off
Basic Card Removal Procedure
Basic Card Insertion Procedure

Quiescing Card and Driver

General
Pausing a Driver (Optional)
Shared Interrupt Must Be Handled Correctly
Quiescing a Driver That Controls Multiple Devices
Quiescing a Failed Card

Driver's Initial Accesses To Card
Treatment of Device ROM
Who Configures the Card?
Efficient Use of Memory and/or IO Space
Slot Identification

Physical Slot ID
Logical Slot ID
PCI Bus Number, Device Number
Translating Slot IDs

Card Sets
The Primitives
Issues Related to PCI RST#
66MHz-Related Issues
Power-Related Issues

Slot Power Requirements
Card Connected To Device With Separate Power Source

Chapter 23: Power Management

Power Management Abbreviated "PM" In This Chapter
PCI Bus PM Interface Specification-But First
A Power Management Primer

Basics of PC PM
OnNow Design Initiative Scheme Defines Overall PM
Goals
Current Platform Shortcomings
No Cooperation Among System Components
Add-on Components Do Not Participate In PM
Current PM Schemes Fail Purposes of OnNow Goals
Installing New Devices Still Too Hard
Apps Generally Assume System Fully On At All Times
System PM States
Device PM States
Definition of Device Context
General
PM Event (PME) Context
Device Class-Specific PM Specifications
Default Device Class Specification
Device Class-Specific PM Specifications
Power Management Policy Owner
General
In Windows OS Environment
PCI Power Management vs....ACPI
PCI Bus Driver Accesses PCI Configuration and PM Registers
ACPI Driver Controls Non-Standard Embedded Devices
Some Example Scenarios
Scenario-Restore Function To Powered Up State
Scenario-OS Wishes To Power Down Bus
Scenario-Setup a Function-Specific System WakeUp Event
PCI Bus PM Interface Specification
Legacy PCI Devices-No Standard PM Method
Device Support for PCI PM Optional
Discovering Function's PM Capability
Power Management-PCI Bus vs....PCI Function
Bridge-Originating Device for a Secondary PCI Bus
PCI Bus PM States
Bus PM State vs. PM State of the PCI Functions On the Bus
Bus PM State Transitions
Function PM States
D0 State-Full On
D0 Uninitialized
D0 Active
D1 State-Light Sleep
D2 State-Deep Sleep
D3-Full Off
D3Hot State
D3Cold State
Function PM State Transitions
Detailed Description of PM Registers
PM Capabilities (PMC) Register
PM Control/Status (PMCSR) Register
Data Register
Determining Presence of Data Register
Operation of the Data Register
Multi-Function Devices
PCI-to-PCI Bridge Power Data
PCI-to-PCI Bridge Support Extensions Register
Detailed Description of PM Events
Two New Pins-PME# and 3.3Vaux
What Is a PM Event?
Example Scenario
Rules Associated With PME#'s Implementation
Example PME# Circuit Design
3.3Vaux
Can a Card With No Power Generate PME#?
Maintaining PME Context in D3cold State
System May or May Not Supply 3.3Vaux
3.3Vaux System Board Requirements
3.3Vaux Card Requirements
Card 3.3Vaux Presence Detection
Problem: In B3 State, PCI RST# Signal Would Float
Solution
OS Power Management Function Calls
Get Capabilities Function Call
Set Power State Function Call
Get Power Status Function Call
BIOS/POST Responsibilities at Startup

Chapter 24: PCI-to-PCI Bridge

Scaleable Bus Architecture
Terminology
Example Systems
Example One
Example Two
PCI-to-PCI Bridge: Traffic Director
Latency Rules
Configuration Registers
General
Header Type Register
Registers Related to Device ID
Introduction
Vendor ID Register
Device ID Register
Revision ID Register
Class Code Register
Bus Number Registers
Introduction
Primary Bus Number Register
Secondary Bus Number Register
Subordinate Bus Number Register
Command Registers
Introduction
Command Register
Bridge Control Register
Status Registers
Introduction
Status Register (Primary Bus)
Secondary Status Register
Introduction To Chassis/Slot Numbering Registers
Address Decode-Related Registers
Basic Transaction Filtering Mechanism
Bridge Memory, Register Set and Device ROM
Introduction
Base Address Registers
Expansion ROM Base Address Register
Bridge's IO Filter
Introduction
Bridge Doesn't Support Any IO Space Behind Bridge
Bridge Supports 64KB IO Space Behind Bridge
Bridge Supports 4GB IO Space Behind Bridge
Legacy ISA IO Decode Problem
Some ISA Drivers Use Alias Addresses To Talk To Card
Problem: ISA and PCI-to-PCI Bridges on Same PCI Bus
PCI IO Address Assignment
Effect of Setting the ISA Enable Bit
Bridge's Memory Filter
Introduction
Determining If Memory Is Prefetchable or Not
Supports 4GB Prefetchable Memory On Secondary Side
Supports > 4GB Prefetchable Memory On Secondary
Rules for Prefetchable Memory
Bridge's Memory-Mapped IO Filter
Cache Line Size Register
Latency Timer Registers
Introduction
Latency Timer Register (Primary Bus)
Secondary Latency Timer Register
BIST Register
Interrupt-Related Registers
Configuration Process
Introduction
Bus Number Assignment
Chassis and Slot Number Assignment
Problem: Adding/Removing Bridge Causes Buses to Be Renumbered
If Buses Added/Removed, Slot Labels Must Remain Correct
Definition of a Chassis
Chassis/Slot Numbering Registers
Introduction
Slot Number Register (read-only)
Chassis Number Register (read/write)
Some Rules
Three Examples
Example One
Example Two
Example Three
Address Space Allocation
IRQ Assignment
Display Configuration
There May Be Two Display Adapters
Identifying the Two Adapters
The Adapters May Be On Same or Different Buses
Solution
PCI-to-PCI Bridge State After Reset
Non-VGA Graphics Controller (aka GFX) After Reset
VGA Graphics Controller After Reset
Effects of Setting VGA's Palette Snoop Bit
Effects of Clearing GFX's Palette Snoop Bit
Effects of Bridge's VGA-Related Control Bits
Detecting and Configuring Adapters and Bridges
Configuration and Special Cycle Filter
Introduction
Special Cycle Transactions
Type 1 Configuration Transactions
Type 0 Configuration Access
Interrupt Acknowledge Handling
PCI-to-PCI Bridge With Subtractive Decode Feature
Reset
Arbitration
Interrupt Support
Devices That Use Interrupt Traces
Devices That Use MSI
Buffer Management
Handling of Memory Write and Invalidate Command
Rules Regarding Posted Write Buffer Usage
Multiple-Data Phase Special Cycle Requests
Error Detection and Handling
General
Handling Address Phase Parity Errors
Introduction
Address Phase Parity Error on Primary Side
Address Phase Parity Error on Secondary Side
Read Data Phase Parity Error
Introduction
Parity Error When Performing Read On Destination Bus
Parity Error When Delivering Read Data To Originating Master
Bad Parity On Prefetched Data
Write Data Phase Parity Error
General
Data Phase Parity Error on IO or Configuration Write
Introduction
Master Request Error
Target Completion Error
Parity Error On a Subsequent Retry
Data Phase Parity Error on Posted Write
Introduction
Originating Bus Error-Pass It Along To Target
Destination Bus Error
Handling Master Abort
Handling Target Abort
Introduction
Target Abort On Delayed Write Transaction
Target Abort On Posted Write
Discard Timer Timeout
Handling SERR# on Secondary Side

Chapter 25: Transaction Ordering & Deadlocks

Definition of Simple Device vs. a Bridge
Simple Device
Bridge
Simple Devices: Ordering Rules and Deadlocks
Ordering Rules For Simple Devices
Deadlocks Associated With Simple Devices
Scenario One
Scenario Two
Bridges: Ordering Rules and Deadlocks
Introduction
Bridge Manages Bi-Directional Traffic Flow
Producer/Consumer Model
General Ordering Requirements
Only Memory Writes Posted
Posted Memory Writes Always Complete In Order
Writes Moving In Opposite Directions Have No Relationship
Before Read Crosses Bridge, Memory Must Be Sync'd Up
Posted Write Acceptance Cannot Depend On Master Completion
Description
Exception To the Rule-Master Has Locked Target
Delayed Transaction Ordering Requirements
Bridge Ordering Rules
Rule 1-Ensures Posted Memory Writes Are Strongly-Ordered
Rule 2-Ensures Just-Latched Read Obtains Correct Data
Rule 3-Ensures DWR Not Done Until All Posted Writes Done
Rule 4-Bi-Directional Posted Writes Done Before Read Data Obtained
Rule 5-Avoids Deadlock Between Old and New Bridges
Rule 6-Avoids Deadlock Between New Bridges
Rule 7-Avoids Deadlock Between Old and New Bridges
Locking, Delayed Transactions and Posted Writes
Lock Passage Is Uni-Directional (Downstream-Only)
Once Locked, Bridge Only Permits Locking Master Access
Actions Taken Before Allowing Lock To Traverse Bridge
After Bridge Locked But Before Secondary Target Locked
After Secondary Target Locked, No Secondary Side Posting
Simplest Design-Bridge Reserved For Locking Master's Use

Chapter 26: The PCI BIOS

Purpose of PCI BIOS
OS Environments Supported
General
Real-Mode
286 Protected Mode (16:16)
386 Protected Mode (16:32)
Today's OSs Use Flat Mode (0:32)
Determining if System Implements 32-bit BIOS
Determining Services 32-bit BIOS Supports
Determining if 32-bit BIOS Supports PCI BIOS Services
Calling PCI BIOS
PCI BIOS Present Call

Chapter 27: Locking

2.2 Spec Redefined Lock Usage
Scenarios That Require Locking
General
EISA Master Initiates Locked Transaction Series Targeting Main Memory
Processor Initiates Locked Transaction Series Targeting EISA Memory
Possible Deadlock Scenario
PCI Solutions: Bus and Resource Locking
LOCK# Signal
Bus Lock: Permissible but Not Preferred
Resource Lock: Preferred Solution
Introduction
Determining Lock Mechanism Availability
Establishing Lock
Locked Bridge Cannot Accept Accesses From Either Side
Unlocked Targets May Be Accessed by any Master On Same PCI Bus
Access to Locked Target by Master Other than Owner: Retry
Continuation and/or End of Locked Transaction Series
Use of LOCK# with 64-bit Addressing
Locking and Delayed Transactions
Summary of Locking Rules
Implementation Rules for Masters
Implementation Rules for Targets

Chapter 28: CompactPCI and PMC

Why CompactPCI?
CompactPCI Cards are PCI-Compatible
Basic PCI/CompactPCI Comparison
Basic Definitions
Standard PCI Environment
Passive Backplane
Compatibility Glyphs
Definition of a Bus Segment
Physical Slot Numbering
Logical Slot Numbering
Connector Basics
Introduction to Front and Rear-Panel IO
Front-Panel IO
Rear-Panel IO
Introduction to CompactPCI Cards
System Card
General
32-bit System Card
64-bit System Card
ISA Bus Bridge
Peripheral Cards
32-bit Peripheral Cards
64-bit Peripheral Card
Design Rules
Connectors
General
Pin Numbering (IEC 1076 versus CompactPCI)
Connector Keying
5V and 3.3V Cards
Universal Cards
32-bit PCI Pinout (J1/P1)
64-bit PCI Pinout (J2/P2)
Rear-Panel IO Pinouts
System and Peripheral Card Design Rules
Card Form Factors
General
3U Cards
6U Cards
Non-PCI Signals
System Card Implementation of IDSELs
Resistors Required on a Card
Series Resistors Required at the Connector Pin
Resistor Required at Peripheral Card's REQ# Driver Pin
Resistor Required at Each System Card Clock Driver Pin
Resistor Required at System Card's GNT# Driver Pin
Placement of Pull-Ups on System Card
System Card Pull-Ups Required on REQ64# and ACK64#
Bus Master Requires Pull-Up on GNT#
Decoupling Requirements
Peripheral Card Signal Stub Lengths
32-bit and 64-bit Stub Lengths
Clock Stub Length
System Card Stub Lengths
32-bit and 64-bit Stub Lengths
Clock Routing
Signal Loading
Peripheral Card Signal Loading
System Card Signal Loading
Card Characteristic Impedance
Connector Shielding
Front Panel and Front Panel IO Connectors
Backplane Design Rules
General
3U Backplane
6U Backplane
Dimensions
Overall Backplane Width
Overall Backplane Height
Connector Keying
System Slot Connector Population
Peripheral Slot Connector Population
Power Distribution
Power Specifications
Power Connections
DEG# and FAL# Interconnect
Power Decoupling
Signaling Environment
Clock Routing
8-Slot Backplane
7-Slot Backplane
Backplane with Six or Fewer Slots
Characteristic Impedance
8-Slot Termination
IDSEL Routing
Background
Backplane AD/IDSEL Interconnect
REQ#/GNT# Routing
Interrupt Line Routing
Backplane Routing of PCI Interrupt Request Lines
Backplane Routing of Legacy IDE Interrupt Request Lines
Non-PCI Signals
Geographical Addressing
Backplane 64-bit Support
Treatment of SYSEN# Signal
Treatment of M66EN Signal
Rear-Panel IO Transition Boards
Dimensions
Connectors Used for Rear-Panel IO
Other Mechanical Issues
Orientation Relative to Front-Panel CompactPCI Cards
Connector Pin Labeling
Connector P2 Rear-Panel IO Pinout
Hot Swap Capability
ENUM# Signal Added In CompactPCI 2.1 Spec
Electrical Insertion/Removal Occurs In Stages
Card Insertion Sequence
Card Removal Sequence
Separate Clock Lines Required
Three Levels of Implementation
Basic Hot-Swap
Installing a New Card
Removing a Card
Full Hot-Swap
High-Availability Hot-Swap
Telecom-Related Issues Regarding Connector Keying
PCI Mezzanine Cards (PMC)
Small Size Permits Attachment to CompactPCI Card
Specifications
Stacking Height and Card Thickness
PMC Card's Connector Area
Front-Panel Bezel
The PMC Connector
Mapping PMC Rear-Panel IO to 3U Rear-Panel IO
Mapping PMC Rear-Panel IO to 6U Rear-Panel IO

Appendix A-Glossary of Terms

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this gives a clear understanding of PCI
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Product Details

ISBN:
9780201309744
Other:
MindShare, Inc.
Author:
Shanley, Tom
Author:
Mindshare
Author:
Anderson, Don
Publisher:
Addison-Wesley Professional
Location:
Reading, MA
Subject:
Programming - General
Subject:
Computer Architecture
Subject:
Networking - General
Subject:
Computer Engineering
Subject:
Microcomputers
Subject:
Computer Architecture - General
Subject:
Systems Architecture - General
Subject:
Microcomputers -- Buses.
Subject:
Engineering-General Engineering
Copyright:
Edition Number:
4
Edition Description:
Trade paper
Series:
PC System Architecture Series
Series Volume:
8
Publication Date:
June 1999
Binding:
TRADE PAPER
Grade Level:
Professional and scholarly
Language:
English
Illustrations:
Yes
Pages:
832
Dimensions:
9.31x7.38x1.65 in. 3.05 lbs.

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Related Subjects

Computers and Internet » Computer Architecture » General
Computers and Internet » Computers Reference » General
Computers and Internet » Networking » General
Engineering » Engineering » General Engineering

PCI System Architecture (Mindshare PC System Architecture) Used Trade Paper
0 stars - 0 reviews
$12.95 In Stock
Product details 832 pages Addison-Wesley Professional - English 9780201309744 Reviews:
"Synopsis" by , PCI System Architecture is a detailed and comprehensive guide to the Peripheral Component Interconnect (PCI) Bus Specification, Intel's technology for fast communication between peripheral devices and the computer processor.

This new edition has been thoroughly updated, reorganized, and expanded to cover the PCI Local Bus Specification version 2.2 and other recent developments, including the new PCI Hot-Plug Specification, changes to the PCI-to-PCI Bridge Architecture Specification, revisions to the PCI Bus Power Management Interface Specification, and the new features of the PCI BIOS Specification.

This book provides clear and concise explanations of the relationship of PCI to the rest of the system and PCI fundamentals, including commands, read and write transfers, memory and I/O addressing, error handling, interrupts, and configuration transactions and registers. In addition, you will find specific information on such key topics as:

  • Hot-Plug Specification
  • Power management
  • CompactPCI
  • The 64-bit PCI Extension
  • 66 MHz PCI Implementation
  • Expansion ROMs
  • PCI-to-PCI Bridge and the PCI BIOS
  • Add-in cards and connectors
  • Bus arbitration
  • Reflected-wave switching
  • Early transaction end
  • Fast back-to-back and stepping

Changes from PCI 2.1 to PCI 2.2 and changes from PCI-to-PCI Bridge Specification 1.0 to 1.1 are visibly highlighted throughout the book so that those familiar with the previous versions can quickly get a handle on new features and functions.

Anyone who designs or tests hardware or software involving the PCI bus will find PCI System Architecture, Fourth Edition a valuable resource for understanding and working with this important technology.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title explains from a programmer's perspective the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

"Synopsis" by , PCI is Intel's local bus standard and the bus continues to be utilized throughout the computer industry. The fourth edition reflects revision 2.2 of the PCI specification, and is very timely. Two of the expected changes are the inclusion of power management and the expansion of the Vital Product Data area. As one of the authors described, "Very important that the engineer work with the latest info".
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