Summer Reading Sale
 
 

Recently Viewed clear list


The Powell's Playlist | June 18, 2014

Daniel H. Wilson: IMG The Powell’s Playlist: Daniel H. Wilson



Like many writers, I'm constantly haunting coffee shops with a laptop out and my headphones on. I listen to a lot of music while I write, and songs... Continue »

spacer
Qualifying orders ship free.
$132.25
New Trade Paper
Ships in 1 to 3 days
Add to Wishlist
available for shipping or prepaid pickup only
Available for In-store Pickup
in 7 to 12 days
Qty Store Section
25 Remote Warehouse Software Engineering- Programming and Languages

Digital Design and Modeling with VHDL and Synthesis

by

Digital Design and Modeling with VHDL and Synthesis Cover

 

Synopses & Reviews

Publisher Comments:

Digital Systems Design with VHDL and Synthesis presents an integrated approach to digital design principles, processes, and implementations to help the reader design much more complex systems within a shorter design cycle. This is accomplished by introducing digital design concepts, VHDL coding, VHDL simulation, synthesis commands, and strategies together.

The author focuses on the ultimate product of the design cycle: the implementation of a digital design. VHDL coding, synthesis methodologies and verification techniques are presented as tools to support the final design implementation. Readers will understand how to apply and adapt techniques for VHDL coding, verification, and synthesis to various situations.

Digital Systems Design with VHDL and Synthesis is a result of K.C. Chang's practical experience in both design and as an instructor. Many of the design techniques and considerations illustrated throughout the chapters are examples of viable designs. His teaching experience leads to a step-by-step presentation that addresses common mistakes and hard-to-understand concepts in a way that eases learning.

Unique features of the book include the following:

  • VHDL code explained line by line to capture the logic behind the design concepts
  • VHDL is verified using VHDL test benches and simulation tools
  • Simulation waveforms are shown and explained to verify design correctness
  • VHDL code is synthesized and commands and strategies are discussed. Synthesized schematics and results are analyzed for area and timing
  • Variations on the design techniques and common mistakes are addressed; Demonstrated standard cell, gate array, and FPGA three design processes
  • Each with a complete design case study
  • Test bench, post-layout verification, and test vector generation processes.

Practical design concepts and examples are presented with VHDL code, simulation waveforms, and synthesized schematics so that readers can better understand their correspondence and relationships.

Book News Annotation:

A practical text substituting the word "hard" for "handy" in the current designer joke that interprets the acronym VHDL as Very Hard Description Language. Chang (design and instruction, The Boeing Corporation) has a sense of humor and also compassion for struggling designers, peppering his comprehensive discussion with plenty of examples and exercises that help clarify topics such as VHDL usage, lexical elements, objects, simulation concepts, sequential statements, subprograms, packages, libraries, writing VHDL for synthesis, and behavioral modeling. Includes design project case studies, illustrations, schemata, and codes.
Annotation c. Book News, Inc., Portland, OR (booknews.com)

Synopsis:

Combines VHDL and synthesis in an easy-to-follow step-by-step sequence. This approach addresses common mistakes and hard-to-understand concepts in a way that eases learning. Digital Design and Modeling with VHDL and Synthesis introduces VHDL with closely related practical design examples, simulation waveforms, and schematics so you can better understand their correspondence and relationship. This book is the result of the K.C. Chang's extensive experience in both design and teaching. Many of the design techniques and design considerations, illustrated throughout the chapters, are examples of real designs.

Synopsis:

Practical design concepts and examples are presented with VHDL code, simulation waveforms, and synthesized schematics so that readers can better understand their correspondence and relationships.

Table of Contents

Chapter 1: INTRODUCTION.

1.1 What Is VHDL?

1.2 VHDL Advantages.

1.3 What Is Logic Synthesis?.

1.4 New Design Methodology.

1.5 Book Overview.

1.6 Exercises.

Chapter 2: VHDL BASICS.

2.1 Lexial Elements, Separators, and Delimiters.

2.2 Identifiers.

2.3 Reserved Words.

2.4 Literals.

2.5 Package and Type.

2.6 Object Declaration.

2.7 Entity and Architecture.

2.8 Predefined Attributes.

2.9 Names and Operators.

2.10 Exercises.

Chapter 3: VHDL MODELLING CONCEPTS.

3.1 The Concept of the Signal.

3.2 Process Concurrency.

3.3 Delta Time.

3.4 Concurrent and Sequential Statements.

3.5 Process Activation by a Signal Event.

3.6 Signal-Valued and Signal-Related Attributes.

3.7 Exercises.

Chapter 4: SEQUENTIAL STATEMENTS.

4.1 Variable Assignment Statement.

4.2 Signal Assignment Statement.

4.3 If Statement.

4.4 Case Statement.

4.5 Loop Statement.

4.6 Next Statement.

4.7 Exit Statement.

4.8 Null Statement.

4.9 Procedure Call Statement.

4.10 Return Statement.

4.11 Assertion Statement.

4.12 Wait Statement.

4.13 Exercises.

Chapter 5: CONCURRENT STATEMENTS.

5.1 Process Statement.

5.2 Assertion Statement.

5.3 Concurrent Procedure Call Statement.

5.4 Conditional Signal Assignment Statement.

5.5 Selected Signal Assignment Statement.

5.6 Component Instantiation Statement.

5.7 Generate Statement.

5.8 Block Statement.

5.9 Exercises.

Chapter 6: SUBPROGRAMS AND PACKAGES.

6.1 Subprogram Declaration.

6.2 Subprogram Body.

6.3 Package Body.

6.4 Package Body.

6.5 Resolution Function.

6.6 Subprogram Overloading.

6.7 Subprogram Return Values and Types.

6.8 Type Casting and Type Qualification.

6.9 Exercises.

Chapter 7: DESIGN UNIT, LIBRARY, AND CONFIGURATION.

7.1 Architecture.

7.2 Entity Declaration.

7.3 Port Map and Generic Map.

7.4 Configuration.

7.5 Design Unit.

7.6 VHDL Library.

7.7 Block and Architecture Attributes.

7.8 Exercises.

Chapter 8: WRITING VHDL FOR SYNTHESIS.

8.1 General Guidelines of VHDL Synthesis.

8.2 Writing VHDL to Infer FlipFlops.

8.3 Writing VHDL to Infer Latches.

8.4 Writing VHDL to Infer Tristate Buffers.

8.5 Writing VHDL to Generate Combinational Circuits.

8.6 Putting Them Together.

8.7 Simulation versus Synthesis Differences.

8.8 Think About Hardware.

8.9 Use of Subprogram.

8.10 Synthesis Process.

8.11 Exercises.

Chapter 9: FINITE STATE MACHINES.

9.1 Finite State Machine Background.

9.2 Writing VHDL for a FSM.

9.3 FSM Initialization.

9.4 FSM Flipflop Output Signal.

9.5 FSM Synthesis.

9.6 Exercises.

Chapter 10: MORE ON BEHAVIOURAL MODELING.

10.1 File Types and File I/O.

10.2 ROM Model.

10.3 Bidirectional Pad Model.

10.4 Attribute Declaration and Attribute Specification.

10.5 Access and Record Type.

10.6 Guarded Block.

10.7 Guarded Signal and Null Waveform.

10.8 Disconnection Specification.

10.9 Writing Efficient VHDL Code.

10.10 Exercises.

Chapter 11: A DESIGN CASE AND TEST BENCH.

11.1 Design Description.

11.2 Writing VHDL Model.

11.3 Another Architecture.

11.4 A Test Bench.

11.5 Another Test Bench.

11.6 Synthesizing the Design.

11.7 Exercises.

Chapter 12: ALU DESIGN.

12.1 ALU Design Requirements.

12.2 Describing ALU with VHDL.

12.3 Improving the Design.

12.4 Simulate the Design with a Test Bench.

12.5 Exercises.

Chapter 13: A DESIGN PROJECT.

13.1 Design Requirements.

13.2 Functional VHDL Implementation.

13.3 VHDL Test Bench.

13.4 Synthesis and Layout.

13.5 Layout Backannotation and Verification.

13.6 VHDL Partitioning.

13.7 Exercises.

Chapter 14: VHDL'93.

14.1 More Regular Syntax.

14.2 Sequential Statements.

14.3 Concurrent Statements.

14.4 New Reserved Words.

14.5 Predifined STANDARD Package.

14.6 Attributes.

14.7 Direct Component Instantiation.

14.8 File and Text I/O.

14.9 Extended Identifier.

14.10 Exercises.

Appendix A: VHDL'87 QUICK REFERENCE.

Appendix B: DECLARATION PART TABLE.

Appendix C: VHDL'93 GRAMMER AND SYNTAX REFERENCE.

Index.

Product Details

ISBN:
9780818677168
Author:
Chang, Kou-Chuan
Publisher:
IEEE Press
Author:
Chang, Kou-Chuan
Author:
Chang, K. C.
Location:
Los Alamitos, Calif. :
Subject:
Engineering - Electrical & Electronic
Subject:
Programming Languages - General
Subject:
Logic Design
Subject:
Computer-aided design
Subject:
VHDL (Computer hardware description language)
Subject:
Very high speed integrated circuits
Subject:
Data Modeling & Design
Subject:
VHDL
Subject:
Electronics - Circuits - General
Subject:
Software Engineering - Programming and Languages
Subject:
Circuit Theory & Design
Copyright:
Series:
Systems
Series Volume:
8
Publication Date:
February 1997
Binding:
TRADE PAPER
Grade Level:
Professional and scholarly
Language:
English
Illustrations:
Yes
Pages:
364
Dimensions:
9.32x7.50x.80 in. 1.38 lbs.

Other books you might like

  1. Guide To VHDL 2ND Edition New Hardcover $180.25
  2. Skew-Tolerant Circuit Design New Trade Paper $84.25

Related Subjects

Computers and Internet » Artificial Intelligence » Fuzzy Logic
Computers and Internet » Database » Design
Computers and Internet » Networking » General
Computers and Internet » Software Engineering » Programming and Languages

Digital Design and Modeling with VHDL and Synthesis New Trade Paper
0 stars - 0 reviews
$132.25 In Stock
Product details 364 pages Wiley-IEEE Computer Society Press - English 9780818677168 Reviews:
"Synopsis" by , Combines VHDL and synthesis in an easy-to-follow step-by-step sequence. This approach addresses common mistakes and hard-to-understand concepts in a way that eases learning. Digital Design and Modeling with VHDL and Synthesis introduces VHDL with closely related practical design examples, simulation waveforms, and schematics so you can better understand their correspondence and relationship. This book is the result of the K.C. Chang's extensive experience in both design and teaching. Many of the design techniques and design considerations, illustrated throughout the chapters, are examples of real designs.
"Synopsis" by , Practical design concepts and examples are presented with VHDL code, simulation waveforms, and synthesized schematics so that readers can better understand their correspondence and relationships.
spacer
spacer
  • back to top
Follow us on...




Powell's City of Books is an independent bookstore in Portland, Oregon, that fills a whole city block with more than a million new, used, and out of print books. Shop those shelves — plus literally millions more books, DVDs, and gifts — here at Powells.com.