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25 Remote Warehouse Microsoft Windows- Windows 95 Applications

Error Control for Network-On-Chip Links

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Error Control for Network-On-Chip Links Cover

 

Synopses & Reviews

Publisher Comments:

As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed to address the reliability problem of on-chip communications. This book focuses on the use of error control codes (ECCs) to improve on-chip interconnect reliability. Coverage includes detailed description of key issues in NOC error control faced by circuit and system designers, as well as practical error control techniques to minimize the impact of these errors on system performance. Provides a detailed background on the state of error control methods for on-chip interconnects; Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links; Examines energy-efficient techniques for integrating multiple error control methods in on-chip interconnects;Introduces various design techniques to tradeoff the reliability and energy consumption of on-chip interconnects, including implementation of low link swing voltage and dynamic voltage scaling with error control codes, combination of Hamming product codes with type-II hybrid ARQ, and configurable error control codes implementation.

Synopsis:

This book reviews the state of the art in error control for Network on Chip (NOC) links. It details key issues in NOC error control faced by circuit and system designers as well as practical error control techniques to minimize the impact of these errors.

Synopsis:

This book provides readers with a comprehensive review of the state of the art in error control for Network on Chip (NOC) links.

Table of Contents

Introduction; Interconnect Scaling Trends; Interconnect Errors and Modeling; Networks-on-Chip; Error Control Coding Basics; Common Error Control Codes for On-Chip Interconnect; Concatenated Error Control Codes; Double-Sampling Error Control; Intermittent and Permanent Error Control; Energy-Efficient Hardware Implementation; Future Trends in Error Control.

Product Details

ISBN:
9781441993120
Author:
Ampadu, Paul
Publisher:
Springer
Author:
Fu, Bo
Subject:
Electronics - Circuits - General
Subject:
Embedded Systems
Subject:
Error Control in Network on Chip
Subject:
integrated circuit design
Subject:
network on chip
Subject:
On-chip interconnect
Subject:
Circuits and Systems
Subject:
Computer-Aided Engineering (CAD, CAE) and Design
Subject:
Microsoft Windows-Windows 95 Applications
Copyright:
Edition Description:
2012
Publication Date:
20110831
Binding:
HARDCOVER
Language:
English
Pages:
162
Dimensions:
235 x 155 mm

Related Subjects

Computers and Internet » Operating Systems » Microsoft Windows » Windows 95 » Applications
Engineering » Engineering » CAD
History and Social Science » Sociology » General
Humanities » Philosophy » General
Metaphysics » General
Reference » Science Reference » Technology
Science and Mathematics » Electricity » General Electronics

Error Control for Network-On-Chip Links New Hardcover
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$140.25 In Stock
Product details 162 pages Springer - English 9781441993120 Reviews:
"Synopsis" by , This book reviews the state of the art in error control for Network on Chip (NOC) links. It details key issues in NOC error control faced by circuit and system designers as well as practical error control techniques to minimize the impact of these errors.
"Synopsis" by , This book provides readers with a comprehensive review of the state of the art in error control for Network on Chip (NOC) links.
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