Using Machine-Learning to Efficiently Explore the Architecture/Compiler Co-Design Space

Designing new microprocessors is a time consuming task. Architects rely on slow simulators to evaluate performance and a significant proportion of the design space has to be explored before an implementation is chosen. This process becomes more time consuming when compiler optimisations are also considered. Once the architecture is selected, a new compiler must be developed and tuned. What is needed are techniques that can speedup this whole process and develop a new optimising compiler automatically. This thesis proposes the use of machine-learning techniques to address architecture/compiler co-design. First, two performance models are developed and are used to efficiently search the design space of amicroarchitecture. These models accurately predict performance metrics such as cycles or energy, or a tradeoff of the two. The first model uses just 32 simulations to model the entire design space of new applications, an order of magnitude fewer than state-of-the-art techniques. The second model addresses offline training costs and predicts the average behaviour of a complete benchmark suite. Compared to state-of-the-art, it needs five times fewer training simulations when applied to the SPEC CPU 2000 and MiBench benchmark suites. Next, the impact of compiler optimisations on the design process is considered. This has the potential to change the shape of the design space and improve performance significantly. A new model is proposed that predicts the performance obtainable by an optimising compiler for any design point, without having to build the compiler. Compared to the state-of-the-art, this model achieves a significantly lower error rate. Finally, a new machine-learning optimising compiler is presented that predicts the best compiler optimisation setting for any new program on any new microarchitecture. It achieves an average speedup of 1.14x over the default best gcc optimisation level. This represents 61% of the maximum speedup available, using just one profile run of the application.

This thesis proposes the use of machine-learning to address architecture/compiler co-design. The techniques developed in represent a new methodology with the potential to speed up the design of new processors and automate the generation of the corresponding optimising compilers, resulting in higher system efficiency and shorter time-to-market.

Designing new microprocessors is a time-consuming task. Architects rely on slow simulators to evaluate performance and a significant proportion of the design space has to be explored before an implementation is chosen. This becomes even more time-consuming when compiler optimisations are considered as part of the design process; once a new architecture is selected, a new compiler must be developed and tuned. This thesis proposes the use of machine-learning to address architecture/compiler co-design. The techniques developed in this work represent a new methodology that has the potential to speed up the design of new processors and automate the generation of the corresponding optimising compilers, resulting in higher system efficiency and shorter time-to-market.