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2 Local Warehouse Computer Architecture- General

Universal Serial Bus System Architec 2ND Edition

by

Universal Serial Bus System Architec 2ND Edition Cover

 

Synopses & Reviews

Publisher Comments:

Universal Serial Bus System Architecture, Second Edition, based on the 2.0 version of the Universal Serial Bus specification, provides in-depth coverage and a detailed discussion of USB. It focuses on the USB protocol, signaling environment, and electrical specifications, along with the hardware/software interaction required to configure and access USB devices. Key topics include:
  • Hot plug support (detection of low-, full-, and high-speed devices)
  • Electrical signaling at the 1.5, 12, and 480Mb/s rates
  • 2.0 hub operation (including split transaction support)
  • 2.0 high-speed protocol (including high-bandwidth and ping transactions)
  • High-speed transceiver test modes
  • Suspend/resume operations
  • Device descriptors
  • Device requests (commands)
  • USB transaction protocols (low-, full-, and high-speed)
  • Bus-powered devices
  • Self-powered devices
  • Error detection and handling
  • Device configuration
  • Device classes

This second edition has been updated to reflect the changes in the USB specification from the original 1.0 to the current 2.0. The USB 2.0 specification defines high-speed transactions operating at 480Mb/s that increase throughput by a factor of 40 over the older USB devices. New high-bandwidth, ping, and split transactions have also been added to further increase efficiency of the high-speed protocol. The USB 2.0 specification makes major improvements to USB, while maintaining backward compatibility with 1.0 and 1.1 USB devices. If you design or test hardware or software that involves USB, you wouldn't want to miss the important updates in this book. Universal Serial Bus System Architecture, Second Edition, is an essential, time-saving tool.

The accompanying CD-ROM includes an 85-minute USB 2.0 overview video by Don Anderson, featuring an introduction to the basic concepts underlying USB 2.0 bus operation and protocol. Topics covered include terminology, design goals of USB, a review of low- and full-speed operation used by USB 1.0 and 1.1 systems and devices, an introduction to USB 2.0 high-speed transfers, and how USB 2.0 hubs use split transactions to provide backward compatibility to low- and full-speed devices.

The PC System Architecture Series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Each title is designed to illustrate the relationship between the software and hardware and explains thoroughly the architecture, features, and operations of systems built using one particular type of chip or hardware specification.

0201309750B04062001

Description:

System requirements: 200 MHz PC with sound card and speakers.

About the Author

MindShare, Inc. is one of the leading technical training companies in the hardware industry, providing innovative courses for dozens of companies, including Intel, IBM, and Compaq.

Don Anderson is the author of many MindShare books. He passes on his wealth of experience in digital electronics and computer design by training engineers, programmers, and technicians for MindShare.

0201309750AB07142003

Table of Contents

About This Book.

The MindShare Architecture Series.

Cautionary Note.

Specifications This Book is Based On.

Organization of This Book.

Who Should Read this Book.

Prerequisite Knowledge.

Documentation Conventions.

Identification of Bit Fields (logical groups of bits or signals).

Visit Our Web Page.

We Want Your Feedback.

I. OVERVIEW OF USB 2.0.

1. Design Goals of USB.

Shortcomings of the Original PC I/O Paradigm.

Limited System Resources.

End User Concerns.

Cost.

The USB Paradigm.

Enhanced System Performance.

Hot Plug and Play Support.

Expandability.

Legacy Hardware/Software Support.

Low Cost.

Summary of Key USB Features.

How to Get the USB Specifications.
2. The Big Picture.

Overview.

USB 1.x Systems and Devices.

Low-Speed and Full-Speed Devices.

How Transactions Are Generated.

Sharing the Bus.

Bandwidth Consideration Summary.

2.0 Systems and Devices.

Low-Speed and Full-Speed Devices in a 2.0 System.

High-Speed Devices in a 2.0 System.

High-Speed Bandwidth Summary.

The Players.

USB Client Drivers.

USB Bus Driver.

USB Host Controller Driver.

USB Host Controller/Root Hub.

USB Hubs.

USB Devices.

USB Communications Model.

Communications Flow.

Transfers, IRPs, Frames, and Packets.

Device Framework (how devices present themselves to software).

Device Descriptors.

Device Framework.

USB Peripheral Connection.

Full-Speed Hubs.

High-Speed Hubs.

Topology.
3. Cables and Connectors.

The Connectors.

Series A Connectors.

Series B Connectors.

Cables.

Low-Speed Cables.

Full- and High-Speed Cables.

Cable Power.

Electrical and Mechanical Specifications.
4. USB Cable Power Distribution.

USB Power.

Hubs.

Current Budget.

Over-Current Protection.

Voltage Drop Budget.

Power Switching.

Bus-Powered Hubs.

Power During Hub Configuration.

Bus-Powered Hub Attached to 500ma Port.

Bus-Powered Hub Attached to 100ma Port.

Bus-Powered Hub Attached to Port with >100ma but <500ma.

Current Limiting.

Bus-Powered Devices.

Low-Power Devices.

High-Power Devices.

Self-Powered Hubs.

Power During Configuration.

Current Limiting.

Self-Powered Devices.

Power During Configuration.

II. LOW- & FULL-SPEED DEVICE OPERATION.

5. LS/FS Signaling Environment.

Overview.

Detecting Device Attachment and Speed Detect.

Full-Speed Device Connect.

Low-Speed Device Connect.

Detecting Device Disconnect.

Bus Idle.

Device RESET.

Differential Signaling.

Differential Drivers.

Differential Receivers.

Start of Packet (SOP).

End of Packet (EOP).

Single-Ended Receivers.

NRZI Encoding.

Bit Stuffing.

Summary of USB Signaling States.
6. LS/FS Transfer Types & Scheduling.

Overview.

Client Initiates Transfer.

Communications Pipes.

Communication Initiated by I/O Request Packets.

Frame-Based Transfers.

Transfer Types.

Isochronous Transfers.

Establishing Synchronous Connections.

The Feedback/Feed Forwarding Solution.

Interrupt Transfers.

Control Transfers.

Bulk Transfers.
7. Packets & Transactions.

Overview.

Packets—The Basic Building Blocks of USB Transactions.

Synchronization Sequence.

Packet Identifier.

Packet-Specific Information.

Cyclic Redundancy Checking (CRC).

End of Packet (EOP).

Token Packets.

SOF Packet.

IN Packet.

OUT Packet.

SETUP Packet.

Data Packets—DATA0 and Data1.

Handshake Packets.

Preamble Packet.

Transactions.

IN Transactions.

OUT Transactions.

Setup Transactions/Control Transfers.
8. Error Recovery.

Overview.

Packet Errors.

PID Checks.

CRC Errors.

Bit Stuff Errors.

Packet-Related Error Handling.

Bus Time-Out.

False EOPs.

False EOP During Host Transmission.

False EOP During Target Transmission.

Data Toggle Errors.

Data Toggle Procedure Without Errors.

Data Toggle Procedure with Data Packet Errors.

Data Toggle Procedure With Handshake Packet Errors.

Special Case. Data Toggle During Control Transfer.

Babbling Devices.

Loss of Activity (LOA).

Babble/LOA Detection and Recovery.

Frame Timer.

Host to Hub Skew.

Hub Repeater State Machine.

Isochronous Transfers (Delivery Not Guaranteed).

Interrupt Transfer Error Recovery.

Bulk Transfer Error Recovery.

Control Transfer Error Recovery.
9. USB Power Conservation.

Power Conservation—Suspend.

Device Response to Suspend.

Hub Response to Suspend.

Global Suspend.

Initiating Global Suspend.

Resume from Global Suspend.

Selective Suspend.

Initiating Selective Suspend.

Resume from Selective Suspend.

Selective Suspend When Hub is Suspended.

Selective Suspend Followed by Global Suspend.

Resume via Reset.

Hub Frame Timer After Wakeup.

III. HIGH SPEED DEVICE OPERATION.

10. Overview of HS Device Operation.

Overview.

New High-Speed Device Features.

1.x USB Device Support.

The 2.0 Host Controller.
11. The High-Speed Signaling Environment.

Overview.

Detecting High-Speed Device Attachment.

Initial Device Detection.

Device Reset and the Chirp Sequence.

High-Speed Interfaces Idled.

High-Speed Differential Signaling.

Impedance Matching.

High-Speed Driver Characteristics.

High-Speed Idle.

High-Speed Differential Receivers.

High-Speed Driver/Receiver Compliance Testing.

High-Speed Start of Packet & Synchronization Sequence.

High-Speed End of Packet (EOP).

Detection of High-Speed Device Removal.

High-Speed RESET and Suspend.

Signaling RESET.

Signaling Suspend.

Differentiating Between RESET and Suspend.
12. HS Transfers, Transactions, & Scheduling.

Overview.

High-Speed Transaction Scheduling.

Microframes.

Theoretical HS Bandwidth.

Periodic Transfers.

High-Speed Isochronous Transfers.

High-Speed Interrupt Transfers.

High-Bandwidth Transactions.

Non-Periodic Transfers.

High-Speed Bulk Transfers.

High-Speed Control Transfers.

Ping Transactions.
13. HS Error Detection and Handling.

Overview.

High-Speed Bus Time-out.

False EOP.

HS Babbling Device Detection.
14. HS Suspend and Resume.

Overview.

Entering Device Suspend.

Device Resume.

IV. USB 2.0 HUB OPERATION WITH LS/FS/HS DEVICES.

15. HS Hub Overview.

Overview.

USB 2.0 Hub Attached to High-Speed Port.

High-Speed Transactions.

Low- and Full-Speed Transactions.

USB 2.0 Hub Attached to Full-Speed Port.
16. 2.0 Hubs During HS Transactions.

Overview.

High-Speed Hub Repeater.

Receiver Squelch.

Re-clocking the Packet.

Port Selector State Machine.

Elasticity Buffer.

The Repeater State Machine.
17. 2.0 Hubs During LS/FS Transactions.

Overview.

The Structure of Split Transactions.

Isochronous Split Transaction Examples.

Example Split Transactions with Data Verification.

The Split Token Packet.

The Transaction Translator.

The Major Elements of the Transaction Translator.

Split Transaction Scheduling.

Split Transaction Scheduling Example.

Single versus Multiple Transaction Translators.

Periodic Split Transactions.

Periodic Split Transaction Pipeline.

Isochronous OUT Split Transaction Sequence.

Isochronous IN Split Transaction Sequence.

Interrupt Split OUT Transaction Sequence.

Interrupt IN Split Transaction Sequence.

Non Periodic Split Transactions.

Non-Periodic Split Transaction Pipeline.

Bulk/Control Split OUT Transaction Sequence.

Bulk/Control Split IN Transaction Sequence.

V. USB DEVICE CONFIGURATION.

18. Configuration Process.

Overview.

The Configuration Software Elements.

USB Host Controller Driver.

Configuration Software.

Default Control Pipe.

Resource Management.

Device Client Software.

Root Hub Configuration.

Each Device Is Isolated for Configuration.

Reset Forces Device to Default Address (zero).

Host Assigns a Unique Device Address.

Host Software Verifies Configuration.

Configuration Value Is Assigned.

Client Software Is Notified.
19. USB Device Configuration.

Overview.

Summary of Configuration Process.

How Software Detects Device Attachment & Speed.

Polling the Status Change Endpoint.

Getting Port Status.

Resetting the Port.

Reading and Interpreting the USB Descriptors.

The Standard Descriptors.

How Software Accesses the Descriptors.

Device Descriptor.

Device Qualifier Descriptor.

Configuration Descriptors.

Other Speed Configuration Descriptor.

Interface Descriptors.

Endpoint Descriptors.

Device States.

Attached State.

Powered State.

Default State.

Addressed State.

Configured State.

Suspend State.

Client Software Configuration.
20. Hub Configuration.

Configuring the Hub.

The Default Pipe.

The Status Change Pipe.

Reading the Hub's Descriptors.

1.x Hub Descriptors.

Hub's Standard Device Descriptor.

Hub Configuration Descriptor.

Hub Interface Descriptor.

Status Endpoint Descriptor.

Hub Class Descriptor.

High-Speed Capable Hub Descriptors.

Descriptors When Hub Is Operating at Full Speed.

The 2.0 Hub's Class-Specific Descriptor.

Powering the Hub.

Checking Hub Status.

Detecting Hub Status Changes.

Reading the Hub Status Field.

Reading Port Status.

Enabling the Device.

Summary of Hub Port States.
21. Device Classes.

Overview.

Device Classes.

Audio Device Class.

Standard Audio Interface Requirements.

Synchronization Types.

Audio Class-Specific Descriptors.

Audio Class-Specific Requests.

Communications Device Class.

Communications Device Interfaces.

Communications Class-Specific Descriptors.

Communications Class-Specific Requests.

Display Device Class.

The Standard Display Device Class Interface.

Display Device-Specific Descriptors.

Device-Specific Requests.

Mass Storage Device Class.

Standard Mass Storage Interface.

General Mass Storage Subclass.

CD-ROM Subclass.

Tape Subclass.

Solid State Subclass.

Class- and Device-Specific USB Requests.

VI. USB SOFTWARE OVERVIEW.

22. Overview of USB Host Software.

USB Software.

Function Layer.

Device Layer.

Interface Layer.

The Software Components.

USB Driver (USBD).

Configuration Management.

USB Elements Requiring Configuration.

Allocating USB Resources.

Data Transfer Management.

Providing Client Services (The USB Driver Interface).

Pipe Mechanisms.

Command Mechanisms.

VII. APPENDIX.

Appendix A. Standard Device Requests.

Overview.

Standard Device Requests.

Set/Clear Feature.

Device Remote Wakeup.

Endpoint Stall.

Set/Get Configuration.

Set/Get Descriptor.

Set/Get Interface.

Get Status.

Device Status.

Endpoint Status.

Sync Frame.

Device Tests.

High-speed Driver/Receiver Compliance Testing.
Appendix B. Hub Requests.

Overview.

Hub Request Types.

Standard Requests and Hub Response.

Hub Class Requests.

Get/Set Descriptor Request.

Get Hub Status Request.

Hub Status Fields.

Hub State Change Fields.

Set/Clear Hub Feature Request.

Hub Local Power Change Request.

Hub Over-Current Change Request.

Get Port Status Request.

Port Status Fields.

Port Change Fields.

Set/Clear Port Feature.

Port Test Modes.

Get Bus State.
Appendix C. Universal Host Controller.

Overview.

Universal Host Controller Transaction Scheduling.

Universal Host Controller Frame List Access.

UHC Transfer Scheduling Mechanism.

Bus Bandwidth Reclamation.

Transfer Descriptors.

Queue Heads.

UHC Control Registers.
Appendix D. Open Host Controller.

Overview.

Open Host Controller Transfer Scheduling.

The Open Host Controller Transfer Mechanism.

The ED and TD List Structure.

Interrupt Transfer Scheduling.

Endpoint Descriptors.

Transfer Descriptors.

General Transfer Descriptor.

Isochronous Transfer Descriptor.

The Open Host Controller Registers.
Index. 0201309750T04062001

Product Details

ISBN:
9780201309751
Manufactured:
MindShare, Inc.
Author:
Dzatko, Dave
Manufactured by:
MindShare, Inc.
Manufactured:
MindShare, Inc.
Author:
Mindshare
Author:
Anderson, Don
Publisher:
Addison-Wesley Professional
Location:
Boston
Subject:
Computer Architecture
Subject:
Computer Engineering
Subject:
USB (Computer bus)
Subject:
Integrated software packages
Subject:
Computer Architecture - General
Subject:
USB
Subject:
Systems Architecture - General
Copyright:
Edition Number:
2
Edition Description:
Trade paper
Series:
PC System Architecture Series
Series Volume:
report no. 01-01
Publication Date:
April 2001
Binding:
OTHER
Grade Level:
Professional and scholarly
Language:
English
Illustrations:
Yes
Pages:
544
Dimensions:
24 cm. +

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