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25 Remote Warehouse Microsoft Windows- Windows 95 Applications

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Static Timing Analysis for Nanometer Designs: A Practical Approach

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Static Timing Analysis for Nanometer Designs: A Practical Approach Cover

 

Synopses & Reviews

Publisher Comments:

The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts. The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology. This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.

Synopsis:

This reference on static timing analysis for semiconductors proceeds from simple to complex and covers such topics as cell timing and power modeling, delay calculation and crosstalk. Each topic includes theoretical background and detailed examples.

Synopsis:

Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats. This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful. Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.

Table of Contents

Introduction.- STA Concepts.- Standard Cell Library.- Interconnect Parasitics.- Delay Calculation.- Noise and Crosstalk.- Configuring the Environment: Preparing for STA.- Timing Verification.- Interface Analysis.- Robust Verification.

Product Details

ISBN:
9781441947154
Author:
Bhasker, J.
Publisher:
Springer
Author:
Chadha, Rakesh
Location:
Boston, MA
Subject:
Microsoft Windows-Windows 95 Applications
Subject:
Electronics - Circuits - General
Subject:
CMOS
Subject:
Cell Library
Subject:
Crosstalk.
Subject:
Parasitics
Subject:
STA Concepts
Subject:
Timing
Subject:
Verification
Subject:
Circuits and Systems
Subject:
Electronics and Microelectronics, Instrumentation
Subject:
Computer-Aided Engineering (CAD, CAE) and Design
Subject:
Engineering
Subject:
B
Subject:
Systems engineering
Subject:
Electronics
Subject:
Computer-aided design
Copyright:
Edition Description:
2009
Publication Date:
20120331
Binding:
TRADE PAPER
Language:
English
Pages:
592
Dimensions:
235 x 155 mm

Related Subjects

Computers and Internet » Operating Systems » Microsoft Windows » Windows 95 » Applications
Engineering » Engineering » CAD
Science and Mathematics » Electricity » General Electricity
Science and Mathematics » Electricity » General Electronics

Static Timing Analysis for Nanometer Designs: A Practical Approach New Trade Paper
0 stars - 0 reviews
$219.75 In Stock
Product details 592 pages Springer - English 9781441947154 Reviews:
"Synopsis" by , This reference on static timing analysis for semiconductors proceeds from simple to complex and covers such topics as cell timing and power modeling, delay calculation and crosstalk. Each topic includes theoretical background and detailed examples.
"Synopsis" by , Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats. This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful. Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.
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