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Logical Effort : Designing Fast Cmos Circuits (99 Edition)

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Logical Effort : Designing Fast Cmos Circuits (99 Edition) Cover

 

Synopses & Reviews

Please note that used books may not include additional media (study guides, CDs, DVDs, solutions manuals, etc.) as described in the publisher comments.

Publisher Comments:

Designers of high-speed integrated circuits face a bewildering array of choices and too often spend frustrating days tweaking gates to meet speed targets. Logical Effort: Designing Fast CMOS Circuits makes high speed design easier and more methodical, providing a simple and broadly applicable method for estimating the delay resulting from factors such as topology, capacitance, and gate sizes.

The brainchild of circuit and computer graphics pioneers Ivan Sutherland and Bob Sproull, "logical effort" will change the way you approach design challenges. This book begins by equipping you with a sound understanding of the method's essential procedures and concepts-so you can start using it immediately. Later chapters explore the theory and finer points of the method and detail its specialized applications.

* Explains the method and how to apply it in two practically focused chapters.

* Improves circuit design intuition by teaching simple ways to discern the consequences of topology and gate size decisions.

* Offers easy ways to choose the fastest circuit from among an array of potential circuit designs.

* Reduces the time spent on tweaking and simulations-so you can rapidly settle on a good design.

* Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.

* Presents a complete derivation of the method-so you see how and why it works.

Synopsis:

tweaking and simulations-so you can rapidly settle on a good design.

  • Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.

  • Presents a complete derivation of the method-so you see how and why it works.

  • Synopsis:

    lete derivation of the method-so you see how and why it works.

    Description:

    Includes bibliographical references (p. [233]) and index.

    About the Author

    Ivan E. Sutherland, a vice president and fellow at Sun Microsystems, received the Turing Award and the Von Neumann Medal for his pioneering contributions in the fields of computer graphics and microelectronic design.

    Robert F. Sproull is an internationally noted expert on the design of graphics hardware and software. He too is a vice president and fellow at Sun.David Money Harris is an associate professor of engineering at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Evans & Sutherland, and other design companies. David’s passions include teaching, building chips, and exploring the outdoors. When he is not at work, he can usually be found hiking, mountaineering, or rock climbing. He particularly enjoys hiking with his son, Abraham, who was born at the start of this book project. David holds about a dozen patents and is the author of three other textbooks on chip design, as well as two guidebooks to the Southern California mountains.

    Harvey Mudd College

    Table of Contents

    1 The Method of Logical Effort

    2 Design Examples

    3 Deriving the Method of Logical Effort

    4 Calculating the Logical Effort of Gates

    5 Calibrating the Model

    6 Asymmetric Logic Gates

    7 Unequal Rising and Falling Delays

    8 Circuit Families

    9 Forks of Amplifiers

    10 Branches and Interconnect

    11 Wide Structures

    12 Conclusions

    A Cast of Characters

    B Reference process parameters

    C Logical Effort Tools

    D Solutions

    Product Details

    ISBN:
    9781558605572
    Author:
    Sutherland, Ivan E.
    Author:
    Sproull, Robert F.
    Author:
    Sutherland, Ivan E.
    Author:
    Harris, Sproull, Sutherland, Ivan, Robert F., David
    Author:
    Harris, Sproull, Sutherland, Ivan, Robert, David
    Author:
    Harris, David
    Publisher:
    Morgan Kaufmann Publishers
    Location:
    San Francisco, Calif.
    Subject:
    Engineering - Electrical & Electronic
    Subject:
    Logic, symbolic and mathematical
    Subject:
    Electronics - Circuits - General
    Subject:
    Computer Architecture
    Subject:
    Electronics - Semiconductors
    Subject:
    Logic Design
    Subject:
    Metal oxide semiconductors, Complementary
    Subject:
    Logic devices.
    Subject:
    Delay faults
    Subject:
    Electricity
    Subject:
    Electricity-General Electricity
    Series:
    The Morgan Kaufmann Series in Computer Architecture and Design
    Publication Date:
    19990231
    Binding:
    TRADE PAPER
    Language:
    English
    Illustrations:
    Yes
    Pages:
    256
    Dimensions:
    9.19x7.39x.41 in. .90 lbs.

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    Logical Effort : Designing Fast Cmos Circuits (99 Edition) Used Trade Paper
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    $62.00 In Stock
    Product details 256 pages Morgan Kaufmann Publishers - English 9781558605572 Reviews:
    "Synopsis" by , tweaking and simulations-so you can rapidly settle on a good design.

  • Offers in-depth coverage of specialized areas of application for logical effort: skewed or unbalanced gates, other circuit families (including pseudo-NMOS and domino), wide structures such as decoders, and irregularly forking circuits.

  • Presents a complete derivation of the method-so you see how and why it works.

  • "Synopsis" by , lete derivation of the method-so you see how and why it works.
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