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Network Processor Design: Issues and Practicesby Mark A. Franklin
Synopses & Reviews
Mark A. Franklin received his B.A., B.S.E.E. and M.S.E.E. from Columbia University, and his Ph.D. in EE from Carnegie-Mellon University. He is currently at Washington University in St. Louis where he has a joint appointment in Electrical Engineering and Computer Science, and holds the Urbauer Chair in Engineering. He founded and is Director of the Computer and Communications Research Center and until recently was the Director of the Undergraduate Program in Computer Engineering. Dr. Franklin is engaged in research, teaching and consulting in the areas of computer and communications architectures, ASIC and embedded processor design, parallel and distributed systems, and systems performance evaluation. He is a Fellow of the IEEE, a member of the ACM, and has been an organizer and reviewer for numerous professional conferences including the HPCA8 Workshop on Network Processors (2002). He has been Chair of the IEEE TCCA (Technical Committee on Computer Architecture), and Vice-Chairman of the ACM SIGARCH (Special Interest Group on Computer Architecture).
Patrick Crowley is currently a Ph.D. candidate in the Department of Computer Science and Engineering at the University of Washington. Before arriving in Seattle, he earned a B.A. degree, summa cum laude, from Illinois Wesleyan University where he studied Mathematics, Physics and Computer Science. Crowley's research interests are in the area of computer systems architecture, with a present focus on the design and analysis of programmable packet processing systems. He is an active participant in the architecture research community and a reviewer for several conferences (ASPLOS, ISCA) and journals (IEEE TOCS). He was an organizer and member of the program committee of the HPCA8 Workshop on Network Processors (2002). Upon completing his Ph.D., Crowley intends to pursue a university research and teaching career.
Haldun Hadimioglu received his BS and MS degrees in Electrical Engineering at Middle East Technical University, Ankara Turkey and his Ph.D. in Computer Science from Polytechnic University in New York. He is currently an Industry Associate Professor in the Computer Science Department and a member of the Computer Engineering faculty at the Polytechnic University. He worked as a research engineer at PETAS, Ankara Turkey (1980-1982). Dr. Hadimioglu's research and teaching interests include Computer Architecture, Parallel and Distributed Systems, Networking and VLSI Design. He was a guest editor of the special issue on "Advances in High Performance Memory Systems," IEEE Transactions on Computers (Nov 2001) and has reviewed papers for leading journals such as the IEEE Transactions on Computers. Hadimioglu is a member of the IEEE, the ACM, and Sigma Xi. He has been an organizer of various workshops including, the ISCA Memory Wall (2000), ISCA Memory Performance Issues (2002, 2001) and HPCA8 Workshop on Network Processors (2002). He received Dedicated Faculty and Outstanding Faculty awards from Polytechnic students in 1995 and 1993, respectively.
Peter Z. Onufryk received his B.S.E.E. from Rutgers University, M.S.E.E. from Purdue University, and Ph.D. in Electrical and Computer Engineering from Rutgers University. He is currently a director in the Internetworking Products Division at Integrated Device Technology, Inc. where he is responsible for architecture definition and validation of communications products. Before joining IDT, Peter was a researcher for thirteen years at AT&T Labs - Research (formally AT&T Bell Labs) where he worked on communications systems and parallel computer architectures. These included a number of parallel, cache-coherent multiprocessor and dataflow based machines that were targeted towards high performance military systems. Other work there focused on packet telephony and early network processors. Onufryk is a member of the IEEE. He was an organizer and program committee member of the HPCA8 Workshop on Network Processors 2002. Peter was the architect of four communications processors as well as numerous ASICs, boards, and systems.
The past few years have seen significant change in the landscape of high-end network processing. In response to the formidable challenges facing this emerging field, the editors of this series set out to survey the latest research and practices in the des
Table of Contents
1. Network Processors: New Horizons — Patrick Crowley, Mark A. Franklin, Haldun Hadimioglu, Peter Z. Onufryk — 2. Supporting Mixed Real-Time Workloads in — Multithreaded Processors with Segmented — Instruction Caches — Patrick Crowley — 3. Efficient Packet Classification with Digest Caches — Francis Chang, Wu-chang Feng, Wu-chi Feng, Kang Li — 4 Towards a Flexible Network Processor Interface for — RapidIO, Hypertransport, and PCI-Express — Christian Sauer, Matthias Gries, Kurt Keutzer, Jose Ignacio Gomez — 5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet — Yatin Hoskote, Sriram Vangal, Vasantha Erraguntla, Nitin Borkar — 6. A Hardware Platform for Network Intrusion Detection and Prevention — Chris Clark, Wenke Lee, David Schimmel, Didier Contis, Mohamed Koň, Ashley Thomas — 7. Packet Processing on a SIMD Stream Processor — Jathin S. Rai, Yu-Kuen Lai, Gregory T. Byrd — 8. A Programming Environment for Packet-Processing — Systems: Design Considerations — Harrick Vin, Jayaram Mudigonda, Jamie Jason, Erik J. Johnson, Roy Ju, Aaron Kunze, Ruiqi Lian — 9. RNOSA Middleware Platform for Low-Cost — Packet-Processing Devices — Jonas Greutert, Lothar Thiele — 10. On the Feasibility of Using Network Processors for DNA Queries — Herbert Bos, Kaiming Huang — 11. Pipeline Task Scheduling on Network Processors — Mark A. Franklin, Seema Datar — 12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs — Matthias Grünewald, J̲rg-Christian Niemann, Mario Porrmann, Ulrich Rückert — 13. Application Analysis and Resource Mapping — for Heterogeneous Network Processor Architectures — Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf — References — Index.
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