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Guests | May 6, 2013
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Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoCby Marcello Coppola
Synopses & ReviewsPublisher Comments:Written by leading experts in the field, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC comprehensively examines the current state-of-the-art and future trends in multiprocessor system-on-chip (MPSoC), in particular network-on-chip (NoC) design. Incorporating simple methods with easy-to-understand examples, this book considers a wealth of important theoretical and practical topics, such as technological deep sub-micron effects, generic NoC components, topological properties, embeddings of common communication patterns, and system-level design. A complementary CD-ROM features a practical NoC training approach based on the award-winning OCCN environment.
Table of ContentsTowards Multicores: Technology and Software Complexity. On-Chip Bus vs Network-on-Chip. NoC Topology. The Spidergon STNoC. SoC and NoC Design Methodology and Tools. Conclusions and Future Work.
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Computers and Internet » Computer Architecture » General
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