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Vlsi Test Principles and Architectures : Design for Testability (06 Edition)

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Vlsi Test Principles and Architectures : Design for Testability (06 Edition) Cover

 

Synopses & Reviews

Please note that used books may not include additional media (study guides, CDs, DVDs, solutions manuals, etc.) as described in the publisher comments.

Publisher Comments:

This book is a fundamental VLSI Testing and Design-for-Testability (DFT) textbook allowing undergraduates, DFT practitioners, and VLSI designers to learn quickly the basic VLSI Test concepts, principles, and architectures, for test and diagnosis of digital, memory, and analog/mixed-signal designs. VLSI Testing is very basic to the semiconductor industry and is something that almost everyone in the industry needs to have some knowledge of. It is often not sufficiently covered in undergraduate curricula; therefore this book fill the gap in this area for both students and professionals in semiconductor manufacturing, design, systems, electronic design automation (EDA), etc. As 100 million transistor designs are now common, test costs are 25-40% of the overall cost of manufacturing a chip and how a chip is designed greatly impacts the cost of test. As such, it is important for designers and managers to understand the concepts and principles of testing and design-for-test techniques.

• Covers the entirespectrum of VLSI testing from digital, analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.

• Discusses future test technology trends and challenges facing the nanometer design era.

• Companion CD-ROM contains a version of SynTest’s software for student use.

Synopsis:

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

Most up-to-date coverage of design for testability.

Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.

Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

Lecture slides for Chapters 1-12 and exercise solutions for Chapters 1-7 & 10-11 are available now.

Exercise solutions for Chapters 8 & 9 will be available by October 15, 2006.

Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Synopsis:

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

• Most up-to-date coverage of design for testability.

• Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.

• Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

• Lecture slides for Chapters 1-5 and exercise solutions for Chapters 1, 2, 3 & 5 are available now.

• Lecture slides and exercise solutions for the remaining chapters will be available by September 15, 2006.

Synopsis:

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability.

· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.

· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

· Lecture slides and exercise solutions for all chapters are now available.

· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

About the Author

Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).

Kyushu Institute of Technology, Fukuoka, Japan.

Table of Contents

The most up-to-date coverage available of VLSI Testing and Design-for-Testability!

Product Details

ISBN:
9780123705976
Author:
Wang, Laung-terng
Publisher:
Morgan Kaufmann Publishers
Author:
Wu, Cheng-wen.
Author:
Wen, Wu, Wang, Laung-Terng, Cheng-Wen, Xiaoqing
Author:
Wang, Laung-Terng
Author:
Wang, Laung-Terng
Author:
Wen, Xiaoqing
Author:
Wu, Cheng-Wen
Subject:
Engineering - Electrical & Electronic
Subject:
Design
Subject:
Computer Engineering
Subject:
Integrated circuits
Subject:
Electronics - Circuits - VLSI
Subject:
Computer Architecture
Subject:
Engineering / Electrical
Subject:
Electricity
Subject:
Electricity-General Electricity
Edition Description:
Hardcover
Series:
Morgan Kaufmann Series in Systems on Silicon
Publication Date:
20060631
Binding:
HARDCOVER
Language:
English
Pages:
808
Dimensions:
9.25 x 7.5 in

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Vlsi Test Principles and Architectures : Design for Testability (06 Edition) Used Trade Paper
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$68.00 In Stock
Product details 808 pages Morgan Kaufmann Publishers - English 9780123705976 Reviews:
"Synopsis" by , This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

Most up-to-date coverage of design for testability.

Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.

Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

Lecture slides for Chapters 1-12 and exercise solutions for Chapters 1-7 & 10-11 are available now.

Exercise solutions for Chapters 8 & 9 will be available by October 15, 2006.

Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

"Synopsis" by , This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

• Most up-to-date coverage of design for testability.

• Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.

• Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

• Lecture slides for Chapters 1-5 and exercise solutions for Chapters 1, 2, 3 & 5 are available now.

• Lecture slides and exercise solutions for the remaining chapters will be available by September 15, 2006.

"Synopsis" by , This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability.

· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.

· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

· Lecture slides and exercise solutions for all chapters are now available.

· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

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