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Other titles in the Prentice Hall Series in Innovative Technology series:
Mosfet Modeling With Spice (97 Edition)by Daniel Foty
Synopses & ReviewsPlease note that used books may not include additional media (study guides, CDs, DVDs, solutions manuals, etc.) as described in the publisher comments.
This book will help CMOS circuit designers make the best possible use of SPICE models, and will prepare them for new models that may soon be introduced. Introduces SPICE modeling and its use in CMOS circuit design. Presents the formalism of model building and the semiconductor physics of MOS structures. Covers each important SPICE model, showing how to choose the appropriate model. Discusses the popular HSPICE Level 28, as well as Levels 1-3, BSIM 1-3, and MOS Model 9. Presents techniques for accounting for systematic process variations. Describes new model candidates, including the Power-Lane Model, the PCIM Model, and the EKV Model. Includes extensive examples throughout. Practicing engineers and scientists in the semiconductor industry; engineering faculty and students.
Book News Annotation:
Covers all the field-effect transistor (FET) models used in mainstream versions of SPICE, providing a handy reference for the practicing circuit designer. Begins with a discussion of the SPICE circuit simulation environment and the basic physics of semiconductor devices, followed by descriptions of the major FET models: Levels 1,2, and 3; BSIM, BSIM2, and BSIM3; HSPICE Level 28; and MOS Model 9. Following these specifics, device capacitance, process variations, and the correlation of various models with specific hardware are discussed.
Annotation c. Book News, Inc., Portland, OR (booknews.com)
Table of Contents
1. SPICE Modeling and the Dominance of CMOS Technology.
2. SPICE Modeling and the Formalism of Model Building.
3. The Semiconductor Physics of MOS Structures.
4. A Comparison of Analytical and Numerical Results.
5. The Level 1 Model.
6. The Level 2 Model.
7. The Level 3 Model.
9. HSPICE Level 28.
12. MOS Model 9.
13. The Active Device Capacitance.
14. Accounting for Systematic Process Variations.
15. Circuit Level Correlation of Models and Hardware.
16. New Model Candidates.
17. The Future of Device Models for Circuit Simulation.
A. An Executive Summary of the Various Models.
B. Channel Length and Width.
C. The Final Model Equations.
D. The Extracted HSPICE Level 28 Model.
E. The Binned BSIM2 Model.
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