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Other titles in the Kluwer International Series in Engineering & Computer Science series:

System-On-Chip Methodologies & Design Languages

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System-On-Chip Methodologies & Design Languages Cover

 

Synopses & Reviews

Publisher Comments:

System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.

Synopsis:

System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.

Table of Contents

Contributors Preface. VHDL trends. 1. HDLCon'00. VHDL in 2005 - The Requirements; R. Klenke, et al. 2. FDL'00. Application of VHDL Features for Optimization of Functional Validation Quality Measurement; C. López, et al. 3. FDL'99. An Object-Oriented Component Model Using Standard VHDL for Mixed Abstraction Level Design; C. Hansen, et al. 4. FDL'00. A VHDL-Centric Mixed-Language Simulation Environment; A. Windisch, et al. 5. FDL'00. Analogue Circuit Synthesis from VHDL-AMS; T. Kazmierski, F. Hamid. Formal verification. 6. HDLCon'00. Symbolic Simulation & Verification of VHDL with ACL2; D. Borrione, et al. 7. HDLCon'00. Functional Verification with Embedded Checkers; S. Switzer, et al. 8. APChDL'00. Improved Design Verification by Random Simulation Guided by Genetic Algorithms; P. Faye, E. Cerny. 9. APChDL'00. VERIS:An Efficient Model Checker for Synchronous VHDL Designs; F. Yiping, et al. Synthesis. 10. APChDL'00. Title On Flip-flop Inference in HDL Synthesis; H-M. Lin, J-Y. Jou. 11. FDL'00. Synthesis Oriented Communication Design for Structural Hardware Objects; W. Putzke-Röming, W. Nebel. 12. FDL'00. High-Level Synthesis through Transforming VHDL Models; A. Prihozhy. Specification formalisms. 13. FDL'99. Multi-facetted Modeling; P. Alexander, D. Barton. 14. FDL'00. A Dual Spring System Case-Study Model in Rosetta; P. Ashenden, et al. 15. FDL'00. Transformational System Design Based on a Formal Computational Model and Skeletons; W. Wu, et al. 16. FDL'99. Models of Asynchronous Computation; M. Josephs. 17. FDL'99. A Mixed Event-value Based Specification Model for Reactive Systems; N. Fristacky, et al. 18. FDL'00. JESTER: An ESTEREL-based Reactive JAVA Extension for Reactive Embedded Systems; M. Antoniotti, et al. 19. APChDL'00. A Four-phase Handshaking Asynchronous Controller Specification Style and its Idle-Phase Optimization; R. Kazumiti Morizawa, T. Nanya. Tool Performance. 20. HDLCon'00. Automating the Validation of Hardware Description Language Processing Tools; S. Seshadri, et al. 21. APChDL'00. A Retargetable Software Power Estimation Methodology; C. Brandolese. 22. HDLCon'00. Performance Tradeoffs for Emulation, Hardware Acceleration, and Simulation; G. Peterson. 23. HDLCon'00. TCL PLI, a Framework for Reusable, Run Time Configurable Test Benches; S. Voges, M. Andrews. Methods for soc design and re-use. 24. APChDL'00. Object-Oriented Specification and Design of Embedded Hard Real-Time Systems; W. Nebel, et al. 25. HDLCon'00. System Level Design for SOC's; G. Martin, B. Salefski. 26. FDL'00. Virtual Component Reuse and Qualification for Digital and Analogue Design; N. Martínez Madrid, R. Seepold. 27. FDL'00. Interface Based Design Using the VSI System-level Interface Behavioral Documentation Standard; B. Bailey, et al. 28. HDLCon'00 Virtual Component HW/SW Co-Design. From System Level Design Exploration to HW/SW Implementation; F. Schirrmeister, S. Krolikoski.

Product Details

ISBN:
9780792373933
Other:
Ashenden, Peter J.
Publisher:
Springer
Editor:
Ashenden, Peter J.
Editor:
Mermet, J.
Author:
Ashenden, Peter J.
Author:
Mermet, Jean
Author:
Seepold, Ralf
Location:
Boston, MA
Subject:
Engineering - Electrical & Electronic
Subject:
Logic Design
Subject:
Integrated circuits
Subject:
Computer hardware description languages
Subject:
Hardware - Personal Computers - General
Subject:
Electricity
Subject:
Personal Computers & Micro / General
Subject:
Computer: Hardware
Subject:
Computer-Aided Engineering (CAD, CAE) and Design
Subject:
Computing Methodologies.
Subject:
Engineering - General
Subject:
Artificial Intelligence - Fuzzy Logic
Subject:
Output Equipment
Subject:
Computer Science
Subject:
Language, literature and biography
Subject:
Computer-aided design
Subject:
Electronic data processing
Subject:
Engineering
Copyright:
Edition Description:
Book
Series:
Kluwer International Series in Engineering & Computer Science
Series Volume:
no. 197
Publication Date:
20010630
Binding:
HARDCOVER
Language:
English
Illustrations:
Yes
Pages:
352
Dimensions:
235 x 155 mm 1490 gr

Related Subjects

Computers and Internet » Artificial Intelligence » Fuzzy Logic
Computers and Internet » Personal Computers » General
Science and Mathematics » Electricity » General Electricity
Science and Mathematics » Electricity » General Electronics

System-On-Chip Methodologies & Design Languages New Hardcover
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Product details 352 pages Kluwer Academic Publishers - English 9780792373933 Reviews:
"Synopsis" by , System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.
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