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Vhdl : From Simulation To Synthesis - Text Only (01 Edition)by Sudhakar Yalamanchili
Synopses & ReviewsPlease note that used books may not include additional media (study guides, CDs, DVDs, solutions manuals, etc.) as described in the publisher comments.
The book has been written to introduce students and practitioners alike to two important topics:
The road to useful models is paved by language features motivated by the need to describe behavioral and physical properties of digital circuits such as events, propagation delays, and concurrency. In this book, each major language construct is studied from two points of view:
Each language feature presented in the book is accompanied by a complete example. Simulation and synthesis exercises address one or more associated VHDL modeling concepts. Further, the book is packaged with the Xilinx Student Edition Foundation Series Software, producing a powerful and self-contained learning environment. The result of reading this book is a fast paced ascension through the language to productive applications for solving realistic problems.
Practicing engineers will find the text and tool application self-paced. Instructors will find that the style of the book enables it to be used as a companion to courses in digital logic, computer architecture, or a HDL course. The Xilinx Student Edition tool sets enable students to quickly develop intuition about VHDL models. All readers will progress rapidly from reading to creating functioning models.
By focusing on the most commonly used core constructs and providing tutorials with the accompanying Xilinx Student Edition tools, Introductory VHDL: From Simulation To Synthesis is a must for those wishing to rapidly add VHDL to their skill sets.
This book focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by familiarity with digital logic circuits with simulation and synthesis presented as complementary design processes. Field programmable gate arrays are used as the medium for synthesis laboratory exercises, and tutorials are provided for the use of the new integrated design environments from Xilinx—which is available with the book. For engineers interested in Digital Design Laboratory, Digital Design, Advanced Digital Design, and Advanced Digital Logic
Table of Contents
What is VHDL? Digital System Design. The Marketplace. The Role of Hardware Description Languages. Chapter Summary.
2. Modeling Digital Systems.
Motivation. Describing Systems. Events, Propagation Delays, and Concurrency. Waveforms and Timing. Signal Values. Shared Signals. Chapter Summary.
3. Simulation vs. Synthesis.
The Simulation Model. The Synthesis Model. Field Programmable Gate Arrays (FPGAs). Chapter Summary.
4. Basic Language Concepts: Simulation.
Signals. Entity—Architecture. Concurrent Statements. Constructing VHDL Models Using CSAs. Understanding Delays. Chapter Summary.
5. Basic Language Concepts: Synthesis.
A Language Directed View of Synthesis. Inference from Declarations. Inference from Simple Concurrent Signal Assignment Statements. Inference from Conditional Signal Assignment Statements. Inference from Selected Signal Assignment Statements. Simulation Behavior vs. Synthesis Behavior. Synthesis Hints. Summary. Exercises.
6. Modeling Behavior: Simulation.
The Process Construct. Programming Constructs. More on Processes. The Wait Statement. Attributes. Generating Clocks and Periodic Waveforms. Using Signals in a Process. Modeling State Machines. Constructing VHDL Models Using Processes. Common Programming Errors. Chapter Summary.
7. Modeling Behavior: Synthesis.
A Language Directed View of Synthesis. Inference from Within Processes. Miscellaneous Issues. Inference Using Signals vs. Variables. Latch vs. Flip Flop Inference. The Wait Statement. Synthesis of State Machines. Simulation vs., Synthesis Hints. Chapter Summary.
8. Modeling Structure.
Describing Structure. Constructing Structural VHDL Models. Hierarchy, Abstraction, and Accuracy. Generics. Component Instantiation and Synthesis. Configurations. Common Programming Errors. Chapter Summary.
9. Subprograms, Packages, and Libraries.
Essentials of Functions. Essentials of Procedures. Subprogram and Operator Overloading. Essentials of Packages. Essentials of Libraries. Chapter Summary.
10. Basic Input/Output.
Basic Input/Output Operations. The Package TEXTIO. Textbenches in VHDL. ASSERT Statement. A Testbench Template. Chapter Summary.
11. Programming Mechanics.
Terminology and Directory Structure. Simulation Mechanics. Synthesis Mechanics. Chapter Summary.
12. Identifiers, Data Types, and Operators.
Identifiers. Data Objects. Data Types. Operators. Chapter Summary.
A. Synthesis Hints.
B. VHDL 1987 vs. VHDL 1993.
C. Active VHDL Tutorial.
D. Xilinx Foundation Express Tutorial.
E. Synopsys FPGA Express Tutorial.
F. Standard VHDL Packages.
G. A Starting Program Template.
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