Synopses & Reviews
In the decade since the first edition of this book was published, the technologies of digital design have continued to evolve. The evolution has run along two related tracks: the underlying physical technology and the software tools that facilitate the application of new devices. The trends identified in the first edition have continued and promise to continue to do so. Programmable logic is virtually the norm for digital designers and the art of digital design now requires the software skills to deal with hardware description languages.
Hardware designers now spend the majority of their time dealing with software. Specifically, the tools needed to efficiently map digital designs onto the emerging programmable devices that are growing more sophisticated. They capture their design specifications in software with language appropriate for describing the parallelism of hardware; they use software tools to simulate their designs and then to synthesize it into the implementation technology of choice. Design time is radically reduced, as market pressures require products to be introduced quickly at the right price and performance.
Although the complexity of designs is necessitating ever more powerful abstractions, the fundamentals remain unchanged. The contemporary digital designer must have a much broader understanding of the discipline of computation, including both hardware and software. This broader perspective is present in this second edition.
About the Author
Randy Katz received his undergraduate degree from Cornell University, and his M.S. and Ph.D. degrees from the University of California, Berkeley. He joined the faculty at Berkeley in 1983, where he is now the United Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science. He is a Fellow of the ACM and the IEEE, and a member of the National Academy of Engineering and the American Academy of Arts and Sciences. He has published over 230 refereed technical papers, book chapters, and books. He has won numerous awards, including 12 best paper awards, one "test of time" paper award, three best presentation awards, the Outstanding Alumni Award of the Computer Science Division, the CRA Outstanding Service Award, the Berkeley Distinguished Teaching Award, the Air Force Exceptional Civilian Service Decoration, The IEEE Reynolds Johnson Information Storage Award, the ASEE Frederic E. Terman Award, and the ACM Karl V. Karlstrom Outstanding Educator Award. With colleagues at Berkeley, he developed the terminology of and early prototypes for Redundant Arrays of Inexpensive Disks (RAID;. While on leave for government service in 1993-1994, he established whitehouse.gov and connected the White House to the Internet.
Gaetano Borriello is a Professor of Computer Science & Engineering at the University of Washington in Seattle. He received his undergraduate degree from the Polytechnic University, his M.S. degree from Stanford University, and his Ph.D. degree from the University of California, Berkeley. Prior to Berkeley he was a member of the research staff at Xerox's Palo Alto Research Center, where he was one of the designers of the first single-chip integrated Ethernet controller. He joined the faculty at UW in 1988 and received a Distinguished Teaching Award for his contributions in establishing the Computer Engineering undergraduate degree program. His research interests are in the design of ubiquitous computing technologies, the design of the embedded systems that connect the physical and virtual worlds, in the use of wireless sensors to infer human activities, and in creating applications that automatically adapt to their user's context. He is the founding director of Intel Research Seattle, a research laboratory focusing on new technologies and usage models for ubiquitous computing.
Table of Contents
1. Introduction 1.1 Dissecting the Title
1.2 A Brief History of Logic Design
1.3 Computation
1.4 Examples
2. Combinational Logic
2.1 Outputs as a Function of Inputs
2.2 Laws and Theorems of Boolean Logic
2.3 Realizing Boolean Formulas
2.4 Two-Level Logic
2.5 Motivation for Two-Level Simplification
2.6 Multi-level Logic
2.7 Motivation for Multi-Level Minimization
3. Working with Combinational Logic
3.1 Two-Level Simplification
3.2 Automating Two-level Simplification
3.3 Multi-level Simplification
3.4 Automating Multi-level Simplification
3.5 Time Response in Combinational Networks
3.6 Hardware Description Languages
4. Combinational Logic Technologies
4.1 History
4.2 Basic Logic Components
4.3 Two-Level and Multi-Level Logic
4.4 Non-gate Logic
5. Case Studies in Combinational Logic Design
5.1 Design Procedure
5.2 A Simple Process Line Control Problem
5.3 Telephone Keypad Decoder
5.4 Leap Year Calculation
5.5 Logic Function Unit
5.6 Adder Design
5.7 Arithmetic Logic Unit Design
5.8 Combinational Multiplier
6. Sequential Logic
6.1 Sequential Logic Elements
6.2 Timing Methodologies
6.3 Registers
7. Finite State Machines
7.1 Counters
7.2 The Concept of the State Machine
7.3 Basic Design Approach
7.4 Motivation for Optimization
8. Working with Finite State Machines
8.1 State Minimization/Reduction
8.2 State Assignment
8.3 Finite State Machine Partitioning
8.4 Hardware Description Languages
9. Sequential Logic Technologies
9.1 Basic Sequential Logic Components
9.2 FSM Design with Counters
9.3 FSM Design with Programmable Logic
9.4 FSM Design with More Sophisticated Programmable Logic
9.5 Case Study: Traffic Light Controller
10. Case Studies in Sequential Logic Design
10.1 A Finite String Recognizer
10.2 A Complex Counter
10.3 A Digital Combination Lock
10.4 A Memory Controller
10.5 A Sequential Multiplier
10.6 A Serial Line Transmitter/Receiver
11. Computer Organization
11.1 Structure of a Computer
11.2 Busing Strategies
11.3 Finite State Machines for Simple CPUs
12. Controller Implementation
12.1 Random Logic
12.2 Time State (Divide and Conquer)
12.3 Jump Counter
12.4 Branch Sequencers
12.5 Microprogramming
Epilogue