Synopses & Reviews
The term superscalar describes a computer architecture that achieves performance by concurrent execution of scalar instructions. Superscalar architectures represent the next step in the evolution of microprocessors. This book is intended as a technical tutorial and introduction for engineers & computer scientists. The book concentrates on reduced instruction set (RISC) processors.
Intended for engineers, computer scientists and graduate students with a strong background in computer architecture, this technical tutorial concentrates mostly on reduced-instruction-set (RISC) processors, but also deals with complex instruction-set (CISC) processors.
Table of Contents
1. Beyond Pipelining, CISC, and RISC.
2. An Introduction to Superscalar Concepts.
3. Developing an Execution Model.
4. Instruction Fetching and Decoding.
5. The Role of Exception Recovery.
6. Register Dataflow.
7. Out-of-Order Instruction Execution.
8. Memory Dataflow.
9. Complexity and Controversy.
10. Basic Software Scheduling.
11. Software Scheduling Across Branches.
12. Evaluating Alternatives: A Perspective on Superscalar Microprocessors.