Synopses & Reviews
VLSI planarization is one of the basic stages of the so-called topological approach to VLSI design. This book considers the intense recent development in this field. Although it features an analysis of the problem and the results of different authors are classified and generalized, this volume is mainly based on the investigations conducted by the present authors during the last fifteen years. This included work in the field of design and research in mathematical methods applied to the mentioned approach for computer-aided design, and in the field of designing concrete industrial design systems. The theory and methods discussed here may be applied to printed-circuit boards, hybrid circuits, etc. This work concentrates on essentially' hypergraph models of electric circuits and their planarization techniques. It is just this aspect of the topological approach to design that has not been adequately investigated before. Audience: This book will be of interest to theoretical and applied mathematicians whose work involves VLSI design, algorithms, graph theory and complexity theory, and EDA tools developers.
Synopsis
At the beginning we would like to introduce a refinement. The term 'VLSI planarization' means planarization of a circuit of VLSI, Le. the embedding of a VLSI circuit in the plane by different criteria such as the minimum number of connectors, the minimum total length of connectors, the minimum number of over-the-element routes, etc. A connector is designed to connect the broken sections of a net. It can be implemented in different ways depending on the technology. Connectors for a bipolar VLSI are implemented by diffused tun nels, for instance. By over-the-element route we shall mean a connection which intersects the enclosing rectangle of an element (or a cell). The possibility of the construction such connections during circuit planarization is reflected in element models and can be ensured, for example, by the availability of areas within the rectangles where connections may be routed. VLSI planarization is one of the basic stages (others will be discussed below) of the so called topological (in the mathematical sense) approach to VLSI design. This approach does not lie in the direction of the classical approach to automation of VLSI layout design. In the classical approach to computer aided design the placement and routing problems are solved successively. The topological approach, in contrast, allows one to solve both problems at the same time. This is achieved by constructing a planar embedding of a circuit and obtaining the proper VLSI layout on the basis of it."
Description
Includes bibliographical references (p. 173-179) and index.