Synopses & Reviews
The emergence of VHDL as a standard for hardware description languages helped disseminate the use of such languages among IC designers. The creation of the standard however does not mean that all work has ceased. Research continues in the use of the language and on improvements of the standard. This book presents the latest research on four key issues related to the use of VHDL. The first part covers simulation of circuits using VHDL, in which timing and switching are central themes. Part II looks at the combination of synthesis and VHDL in designing circuits. This includes a case study of chip design using silicon 1076. Advances in the formal verification of VHDL designs are given in Part III. This relatively new area in the use of VHDL is developing rapidly into an important issue for speeding the design of circuits. The final part considers modelling issues and system level design. The contributors are based on specially selected papers from the EURO-VHDL conferences in 1990 and 1991. These papers have been updated and expanded to give the reader the very latest state-of-the-art in the use of VHDL for circuit design.
Table of Contents
Preface. Introduction. Evolutionary Processes in Language, Software, and System Design; F.E. Marschner. Part I: Simulation. Timing Constraint Checks in VHDL -- a Comparative Study; F. Liu, A. Pawlak. Using Formalized Timing Diagrams in VHDL Simulation; M. Dufresne, K. Khordoc, E. Cerny. Switch-Level Models in Multi-Level VHDL Simulations; K. Khordoc, M. Biotteau, E. Cerny. Bi-Directional Switches in VHDL Using the 46 Value System; A. Stanculescu. Systems Real Time Analysis with VHDL Generated from Graphical SA-VHDL; M. Sipola, J.-P. Soininen, J. Kivelä. Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design; P. Connors, S. Nayak, J. Kraley, V. Berman. Part II: Synthesis. A VHDL-Driven Synthesis Environment; H. Konuk, F.E. Marschner. VHDL Specific Issues in High Level Synthesis; A. Postula. ASIC Design Using Silicon 1076; R.A. Cottrell. Generating VHDL for Simulation and Synthesis from a High-Level DSP Design Tool; L. Lundberg. Aspects of Optimization and Accuracy for VHDL Synthesis; J. Eliott, P. Harper. Part III: Formal Verifications and Semantics. Symbolic Computation of Hierarchical and Interconnected FSMS; A. Debreil, C. Berthet, A. Jerraya. Formal Semantics of VHDL Timing Constructs; A. Salem, D. Borrione. A Structural Information Model of VHDL; R.A.J. Marshall, H.J. Kahn. Formal Verification of VHDL Descriptions in Boyer-Moore: First Results; D. Borrione, L. Pierre, A. Salem. Developing a Formal Semantic Definition of VHDL; P.A. Wilsey. Part IV: Systems Level Design and Modelling. Approaching System Level Design; F.J. Rammig. Incremental Design -- Application of a Software-Based Method for High-Level Hardware Design with VHDL; A. Hohl. Introducing CASCADE Control Graph in VHDL; C. Le Faou, J. Mermet.