Synopses & Reviews
Hardware correctness is becoming ever more important in the design of computer systems. The authors introduce a powerful new approach to the design and analysis of modern computer architectures, based on mathematically well-founded formal methods which allows for rigorous correctness proofs, accurate hardware costs determination, and performance evaluation. This book develops, at the gate level, the complete design of a pipelined RISC processor with a fully IEEE-compliant floating-point unit. In contrast to other design approaches, the design presented here is modular, clean and complete.
Synopsis
Computer Architecture: Complexity and Correctness develops, at the gate level, the complete design of a pipelined RISC processor with delayed branch, forwarding, hardware interlock, precise maskable nested interrupts, caches, and a fully IEEE-compliant floating point unit. In contrast to other design approaches applied in practice and unlike other textbooks available, the design presented here are modular, clean and complete up to the construction of entire complex machines. The authors' systematically basing their approach on rigorous mathematical formalisms allows for rigorous correctness proofs, accurate hardware costs determination, and performance evaluation as well as, generally speaking, for coverage of a broad variety of relevant issues within a reasonable number of pages. The book is written as a text for classes on computer architecture and related topics and will serve as a valuable source of reference for professionals in hardware design.
Synopsis
The design of computer architecture presented here is modular, clean and complete up to the construction of the entire complex machine. Computer systems, hardware and software correctness is becoming more important, while issues of reliability warrant in the fields of nuclear power plants, air traffic control and health care.
Table of Contents
Introduction; Basics; A Sequential DLX Design; Basic Pipelines; Interrupt Handling; Memory System Design; IEEE Standard; Floating Point Algorithms & Data Paths; Pipelined DLX with FPU; DLX Instruction Set Architecture; Specification of the FDLX Design; Bibliography; Index.