Synopses & Reviews
The task of verification is always larger than the task of the design effort. Why? Because the verification system has to encompass the entire functionality of the device under verification. It has to mimic the real world environment that the device will actual operate in. It needs to catch functional errors. It needs to give feedback information to guide further verification. The design effort proceeds from a design specification. Verification systems need to proceed from a verification plan. A comprehensive document that describes the verification system and all its components. A plan that details how the verification system will be built. With the advent of hardware verification languages, today's verifications systems have grown in complexity making verification plans even more paramount. This book is a practical guide on how to get a verification team jumpstarted into verification success by the joint creation of a verification plan. The book includes: -A detailed five day approach that gives day by day, step by step instructions on how to design and document your verification system. -An introduction to hardware verification languages, their pseudo-random mindset, their enabling methodologies (generation, checking and coverage), and how these effect the development of a verification plan. -Practical guidance in common people issues, formatting decisions and information extraction methods to enhance your verification plan brainstorming sessions. -An appendix full of verification plan examples and support documents.
Review
"In this book, Peet gives every engineer trying to do functional verification a jump-start on getting it under control...His technique...is soundly grounded in the real world, honed through years of experience and practice. If you adopt this approach, it will improve the speed with which verification plans are produced, improve their quality, help eliminate redundant work, and reduce unnecessary work...But wait, there's more. Peet not only tells you how to do it, he tells you why you should do it a certain way, and why Hardware Verification Languages give you an advantage (motivation for you to check out the new techniques and ammunition for your presentations to management)...I have been helped already by what Peet gives in his book. I'm keeping my copy right next to Janick's book." (Glenn Hunt, Texas Instruments)
Synopsis
Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail.
Synopsis
The task of verification is always larger than the task of the design effort. Why? Because the verification system has to encompass the entire functionality of the device under verification. It has to mimic the real world environment that the device will actual operate in. It needs to catch functional errors. It needs to give feedback information to guide further verification. The design effort proceeds from a design specification. Verification systems need to proceed from a verification plan. A comprehensive document that describes the verification system and all its components. A plan that details how the verification system will be built. With the advent of hardware verification languages, today's verifications systems have grown in complexity making verification plans even more paramount. This book is a practical guide on how to get a verification team jumpstarted into verification success by the joint creation of a verification plan. The book includes: -A detailed five day approach that gives day by day, step by step instructions on how to design and document your verification system. -An introduction to hardware verification languages, their pseudo-random mindset, their enabling methodologies (generation, checking and coverage), and how these effect the development of a verification plan. -Practical guidance in common people issues, formatting decisions and information extraction methods to enhance your verification plan brainstorming sessions. -An appendix full of verification plan examples and support documents.
Synopsis
This book is a practical guide on how to get a verification team jumpstarted into verification success by the joint creation of a verification plan. The book includes: -A detailed five day approach that gives day by day, step by step instructions on how to design and document your verification system. -An introduction to hardware verification languages, their pseudo-random mindset, their enabling methodologies (generation, checking and coverage), and how these effect the development of a verification plan. -Practical guidance in common people issues, formatting decisions and information extraction methods to enhance your verification plan brainstorming sessions. -An appendix full of verification plan examples and support documents.